October 2026 main drop: mirror from GitHub (part 2)

crates/jxcl-golden/tests/vectors/002_decrement.golden

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+name: decrement
+program: 02 01 05 00 00 00 00 00 00 00 1A 01 60
+halted: true
+fault: none
+registers: 1=4
+flags: none

crates/jxcl-hardware-test/Cargo.toml

@@ -0,0 +1,15 @@
+[package]
+name = "jxcl-hardware-test"
+version = "0.1.0"
+edition = "2021"
+description = "Golden-file regression tests for generated Verilog/VHDL/netlist, plus the mechanical width/opcode-count cross-check against the ISA schema."
+license = "AGPL-3.0-only OR LicenseRef-Commercial"
+
+[dependencies]
+jxcl-hardware = { path = "../jxcl-hardware" }
+jxcl-isa-schema = { path = "../jxcl-isa-schema" }
+jxcl-hdl = { path = "../jxcl-hdl" }
+jxcl-netlist = { path = "../jxcl-netlist" }
+jxcl-opcodes = { path = "../jxcl-opcodes" }
+jxcl-constants = { path = "../jxcl-constants" }
+jxcl-rtl = { path = "../jxcl-rtl" }

crates/jxcl-hardware-test/README.md

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+# jxcl-hardware-test
+
+Golden-file regression tests for generated Verilog/VHDL/netlist, plus the mechanical width/opcode-count cross-check against the ISA schema.
+
+## Honesty boundary
+
+This is a test-only crate. Nothing in it simulates the generated RTL or
+feeds it to a real Verilog/VHDL/synthesis toolchain -- there is no
+`iverilog`, `verilator`, or `yosys` in this environment (see
+`docs/HARDWARE_LIMITATIONS.md` at the workspace root). "Passes" here
+means: matches a checked-in golden file under `tests/golden/`, or
+matches a structural fact mechanically computed from
+`jxcl-opcodes`/`jxcl-constants`'s real tables/constants -- not "was
+hardware-verified."
+
+**`jxcl-isa-schema` status at the time this crate was written:**
+`jxcl-isa-schema` (this crate's other declared dependency) is still a
+placeholder -- no `IsaSchema` type or `generate`/`check_against_spec`
+methods -- as of this writing. `tests/isa_conformance.rs` therefore
+cross-checks the generated decoder directly against
+`jxcl-opcodes::all_defs()` and `jxcl-constants`'s real constants,
+instead of going through `jxcl-isa-schema`. Once `jxcl-isa-schema`
+lands, that test should be switched to compare against
+`IsaSchema::generate()` instead, without changing what it actually
+asserts (a real `IsaSchema` would itself be generated from the same two
+crates).
+
+## Architecture
+
+**Owns:** The hardware golden files (`tests/golden/`) and the
+ISA-vs-RTL conformance check.
+
+**Category:** hardware · **Source:** new
+
+## Public API
+
+Test-only crate; `render_netlist_text` is exposed only so a `Netlist`
+can be golden-file compared the same way rendered Verilog/VHDL text is.
+
+## Dependencies
+
+Workspace crates:
+
+- `jxcl-hardware`
+- `jxcl-isa-schema` (placeholder as of this writing -- see above)
+- `jxcl-hdl`
+- `jxcl-netlist`
+- `jxcl-opcodes`
+- `jxcl-constants`
+- `jxcl-rtl`
+
+External crates:
+
+*(none)*
+
+## Testing
+
+10 tests total: 2 unit tests for `render_netlist_text`, 4 golden-file
+regression tests (`tests/golden_regression.rs`, comparing
+`jxcl-hardware`'s emitted Verilog/VHDL and a synthesized netlist against
+checked-in files under `tests/golden/`), and 4 ISA conformance tests
+(`tests/isa_conformance.rs`). Run with `cargo test -p
+jxcl-hardware-test`.
+
+## Status
+
+`implemented`, with the `jxcl-isa-schema` cross-check as a documented
+direct-table fallback pending that crate's real implementation.
+
+## License
+
+AGPLv3 / Commercial dual-license. See `LICENSE-AGPL`, `LICENSE-COMMERCIAL`, and `LICENSE-NOTICE` at the repository root.

crates/jxcl-hardware-test/src/lib.rs

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+// Copyright (C) 2026 ERRANT DIGITAL INSTITUTE OF TECHNOLOGY (SEIT NGO) % SNAPKITTY COLLECTIVE
+// SPDX-License-Identifier: AGPL-3.0-only OR LicenseRef-Commercial
+// See LICENSE-AGPL and LICENSE-COMMERCIAL in this repository for license terms.
+
+//! Golden-file regression tests for `jxcl-hardware`'s emitted
+//! Verilog/VHDL/netlist, plus the mechanical width/opcode-count
+//! cross-check against the ISA source of truth.
+//!
+//! # Scope and honesty boundary
+//!
+//! This is a test-only crate: it has no public API of its own beyond
+//! [`render_netlist_text`], a small deterministic text serialization of
+//! a [`jxcl_netlist::Netlist`] used purely so a netlist can be compared
+//! against a checked-in golden file the same way rendered Verilog/VHDL
+//! text is. Nothing in this crate simulates the generated RTL or feeds
+//! it to a real Verilog/VHDL/synthesis toolchain -- there is no
+//! `iverilog`/`verilator`/`yosys` in this environment (see
+//! `docs/HARDWARE_LIMITATIONS.md` at the workspace root). "Passes" here
+//! means: matches a checked-in golden file, or matches a structural fact
+//! mechanically computed from `jxcl-opcodes`/`jxcl-constants`'s real
+//! tables/constants -- not "was hardware-verified."
+//!
+//! ## `jxcl-isa-schema` status at the time this crate was written
+//!
+//! `jxcl-isa-schema` (this crate's other declared dependency, per
+//! `docs/crates.toml`) is still a placeholder -- no `IsaSchema` type, no
+//! `IsaSchema::generate`/`check_against_spec` -- as of this writing. The
+//! `tests/isa_conformance.rs` cross-check in this crate therefore
+//! compares `jxcl-hardware`'s generated decoder directly against
+//! `jxcl-opcodes`/`jxcl-constants`'s real tables/constants, exactly the
+//! way `jxcl-rtl`'s own conformance test does. Once `jxcl-isa-schema`
+//! lands with a real generated schema, that test should be switched to
+//! compare against `IsaSchema::generate()` instead (so this crate is
+//! checking the RTL against the ISA's own schema layer, one level higher
+//! than `jxcl-rtl`'s direct-table check), without changing what it
+//! actually asserts.
+#![forbid(unsafe_code)]
+
+use jxcl_netlist::{GateKind, Netlist};
+
+/// A small, deterministic text serialization of a [`Netlist`]: one line
+/// per gate, sorted by output name so the result doesn't depend on
+/// construction order, in the form `kind(in1, in2, ...) -> output`.
+///
+/// This exists only so a [`Netlist`] (which has no inherent canonical
+/// text form of its own -- it's a structural Rust value, not a hardware
+/// description) can be golden-file tested the same way rendered
+/// Verilog/VHDL text already is. It is not a hardware description
+/// format and nothing reads it back.
+pub fn render_netlist_text(netlist: &Netlist) -> String {
+    let mut lines: Vec<String> = netlist
+        .gates
+        .iter()
+        .map(|g| {
+            let kind = match g.kind {
+                GateKind::And => "AND",
+                GateKind::Or => "OR",
+                GateKind::Not => "NOT",
+                GateKind::Mux => "MUX",
+            };
+            format!("{kind}({}) -> {}", g.inputs.join(", "), g.output)
+        })
+        .collect();
+    lines.sort();
+
+    let mut wires: Vec<String> = netlist
+        .wires
+        .iter()
+        .map(|w| format!("wire {} [{} bits]", w.name, w.width))
+        .collect();
+    wires.sort();
+
+    let mut out = lines.join("\n");
+    if !wires.is_empty() {
+        if !out.is_empty() {
+            out.push('\n');
+        }
+        out.push_str(&wires.join("\n"));
+    }
+    out.push('\n');
+    out
+}
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+    use jxcl_netlist::{Gate, Wire};
+
+    #[test]
+    fn render_netlist_text_is_sorted_and_deterministic() {
+        let net = Netlist::new()
+            .with_gates(vec![
+                Gate::mux("sel", "a", "b", "z"),
+                Gate::not("x", "a_inv"),
+            ])
+            .with_wires(vec![Wire::new("internal", 4)]);
+        let text = render_netlist_text(&net);
+        let expected = "MUX(sel, a, b) -> z\nNOT(x) -> a_inv\nwire internal [4 bits]\n";
+        assert_eq!(text, expected);
+    }
+
+    #[test]
+    fn render_netlist_text_handles_empty_netlist() {
+        let net = Netlist::new();
+        assert_eq!(render_netlist_text(&net), "\n");
+    }
+}

crates/jxcl-hardware-test/tests/golden/core_datapath.v

@@ -0,0 +1,237 @@
+module decoder(
+    input wire [7:0] opcode,
+    output reg valid,
+    output reg [3:0] instr_len
+);
+
+    always @(*) begin
+        case (opcode)
+            8'd0: begin
+                valid = 1'd1;
+                instr_len = 4'd1;
+            end
+            8'd1: begin
+                valid = 1'd1;
+                instr_len = 4'd3;
+            end
+            8'd2: begin
+                valid = 1'd1;
+                instr_len = 4'd10;
+            end
+            8'd3: begin
+                valid = 1'd1;
+                instr_len = 4'd7;
+            end
+            8'd4: begin
+                valid = 1'd1;
+                instr_len = 4'd7;
+            end
+            8'd5: begin
+                valid = 1'd1;
+                instr_len = 4'd2;
+            end
+            8'd6: begin
+                valid = 1'd1;
+                instr_len = 4'd2;
+            end
+            8'd7: begin
+                valid = 1'd1;
+                instr_len = 4'd7;
+            end
+            8'd16: begin
+                valid = 1'd1;
+                instr_len = 4'd3;
+            end
+            8'd17: begin
+                valid = 1'd1;
+                instr_len = 4'd3;
+            end
+            8'd18: begin
+                valid = 1'd1;
+                instr_len = 4'd3;
+            end
+            8'd19: begin
+                valid = 1'd1;
+                instr_len = 4'd3;
+            end
+            8'd20: begin
+                valid = 1'd1;
+                instr_len = 4'd3;
+            end
+            8'd21: begin
+                valid = 1'd1;
+                instr_len = 4'd3;
+            end
+            8'd22: begin
+                valid = 1'd1;
+                instr_len = 4'd3;
+            end
+            8'd23: begin
+                valid = 1'd1;
+                instr_len = 4'd3;
+            end
+            8'd24: begin
+                valid = 1'd1;
+                instr_len = 4'd2;
+            end
+            8'd25: begin
+                valid = 1'd1;
+                instr_len = 4'd2;
+            end
+            8'd26: begin
+                valid = 1'd1;
+                instr_len = 4'd2;
+            end
+            8'd32: begin
+                valid = 1'd1;
+                instr_len = 4'd3;
+            end
+            8'd33: begin
+                valid = 1'd1;
+                instr_len = 4'd3;
+            end
+            8'd34: begin
+                valid = 1'd1;
+                instr_len = 4'd3;
+            end
+            8'd35: begin
+                valid = 1'd1;
+                instr_len = 4'd2;
+            end
+            8'd36: begin
+                valid = 1'd1;
+                instr_len = 4'd3;
+            end
+            8'd37: begin
+                valid = 1'd1;
+                instr_len = 4'd3;
+            end
+            8'd38: begin
+                valid = 1'd1;
+                instr_len = 4'd4;
+            end
+            8'd48: begin
+                valid = 1'd1;
+                instr_len = 4'd3;
+            end
+            8'd49: begin
+                valid = 1'd1;
+                instr_len = 4'd3;
+            end
+            8'd50: begin
+                valid = 1'd1;
+                instr_len = 4'd3;
+            end
+            8'd51: begin
+                valid = 1'd1;
+                instr_len = 4'd3;
+            end
+            8'd52: begin
+                valid = 1'd1;
+                instr_len = 4'd3;
+            end
+            8'd64: begin
+                valid = 1'd1;
+                instr_len = 4'd3;
+            end
+            8'd65: begin
+                valid = 1'd1;
+                instr_len = 4'd3;
+            end
+            8'd80: begin
+                valid = 1'd1;
+                instr_len = 4'd5;
+            end
+            8'd81: begin
+                valid = 1'd1;
+                instr_len = 4'd5;
+            end
+            8'd82: begin
+                valid = 1'd1;
+                instr_len = 4'd1;
+            end
+            8'd83: begin
+                valid = 1'd1;
+                instr_len = 4'd5;
+            end
+            8'd84: begin
+                valid = 1'd1;
+                instr_len = 4'd5;
+            end
+            8'd85: begin
+                valid = 1'd1;
+                instr_len = 4'd5;
+            end
+            8'd86: begin
+                valid = 1'd1;
+                instr_len = 4'd5;
+            end
+            8'd87: begin
+                valid = 1'd1;
+                instr_len = 4'd5;
+            end
+            8'd88: begin
+                valid = 1'd1;
+                instr_len = 4'd5;
+            end
+            8'd89: begin
+                valid = 1'd1;
+                instr_len = 4'd5;
+            end
+            8'd90: begin
+                valid = 1'd1;
+                instr_len = 4'd5;
+            end
+            8'd96: begin
+                valid = 1'd1;
+                instr_len = 4'd1;
+            end
+            8'd97: begin
+                valid = 1'd1;
+                instr_len = 4'd3;
+            end
+            8'd98: begin
+                valid = 1'd1;
+                instr_len = 4'd3;
+            end
+            8'd112: begin
+                valid = 1'd1;
+                instr_len = 4'd8;
+            end
+            8'd113: begin
+                valid = 1'd1;
+                instr_len = 4'd7;
+            end
+            8'd114: begin
+                valid = 1'd1;
+                instr_len = 4'd1;
+            end
+            default: begin
+                valid = 1'd0;
+                instr_len = 4'd0;
+            end
+        endcase
+    end
+
+endmodule
+
+module alu(
+    input wire [63:0] op_a,
+    input wire [63:0] op_b,
+    input wire [7:0] alu_op,
+    output wire [63:0] result
+);
+
+endmodule
+
+module register_file(
+    input wire [4:0] read_addr1,
+    input wire [4:0] read_addr2,
+    output wire [63:0] read_data1,
+    output wire [63:0] read_data2,
+    input wire [4:0] write_addr,
+    input wire [63:0] write_data,
+    input wire write_enable
+);
+
+endmodule

crates/jxcl-hardware-test/tests/golden/core_datapath.vhdl

@@ -0,0 +1,198 @@
+entity decoder is
+    port (
+        opcode : in std_logic_vector(7 downto 0);
+        valid : out std_logic;
+        instr_len : out std_logic_vector(3 downto 0)
+    );
+end entity decoder;
+
+architecture rtl of decoder is
+begin
+    process (all) is
+    begin
+        case opcode is
+            when "00000000" =>
+                valid <= '1';
+                instr_len <= "0001";
+            when "00000001" =>
+                valid <= '1';
+                instr_len <= "0011";
+            when "00000010" =>
+                valid <= '1';
+                instr_len <= "1010";
+            when "00000011" =>
+                valid <= '1';
+                instr_len <= "0111";
+            when "00000100" =>
+                valid <= '1';
+                instr_len <= "0111";
+            when "00000101" =>
+                valid <= '1';
+                instr_len <= "0010";
+            when "00000110" =>
+                valid <= '1';
+                instr_len <= "0010";
+            when "00000111" =>
+                valid <= '1';
+                instr_len <= "0111";
+            when "00010000" =>
+                valid <= '1';
+                instr_len <= "0011";
+            when "00010001" =>
+                valid <= '1';
+                instr_len <= "0011";
+            when "00010010" =>
+                valid <= '1';
+                instr_len <= "0011";
+            when "00010011" =>
+                valid <= '1';
+                instr_len <= "0011";
+            when "00010100" =>
+                valid <= '1';
+                instr_len <= "0011";
+            when "00010101" =>
+                valid <= '1';
+                instr_len <= "0011";
+            when "00010110" =>
+                valid <= '1';
+                instr_len <= "0011";
+            when "00010111" =>
+                valid <= '1';
+                instr_len <= "0011";
+            when "00011000" =>
+                valid <= '1';
+                instr_len <= "0010";
+            when "00011001" =>
+                valid <= '1';
+                instr_len <= "0010";
+            when "00011010" =>
+                valid <= '1';
+                instr_len <= "0010";
+            when "00100000" =>
+                valid <= '1';
+                instr_len <= "0011";
+            when "00100001" =>
+                valid <= '1';
+                instr_len <= "0011";
+            when "00100010" =>
+                valid <= '1';
+                instr_len <= "0011";
+            when "00100011" =>
+                valid <= '1';
+                instr_len <= "0010";
+            when "00100100" =>
+                valid <= '1';
+                instr_len <= "0011";
+            when "00100101" =>
+                valid <= '1';
+                instr_len <= "0011";
+            when "00100110" =>
+                valid <= '1';
+                instr_len <= "0100";
+            when "00110000" =>
+                valid <= '1';
+                instr_len <= "0011";
+            when "00110001" =>
+                valid <= '1';
+                instr_len <= "0011";
+            when "00110010" =>
+                valid <= '1';
+                instr_len <= "0011";
+            when "00110011" =>
+                valid <= '1';
+                instr_len <= "0011";
+            when "00110100" =>
+                valid <= '1';
+                instr_len <= "0011";
+            when "01000000" =>
+                valid <= '1';
+                instr_len <= "0011";
+            when "01000001" =>
+                valid <= '1';
+                instr_len <= "0011";
+            when "01010000" =>
+                valid <= '1';
+                instr_len <= "0101";
+            when "01010001" =>
+                valid <= '1';
+                instr_len <= "0101";
+            when "01010010" =>
+                valid <= '1';
+                instr_len <= "0001";
+            when "01010011" =>
+                valid <= '1';
+                instr_len <= "0101";
+            when "01010100" =>
+                valid <= '1';
+                instr_len <= "0101";
+            when "01010101" =>
+                valid <= '1';
+                instr_len <= "0101";
+            when "01010110" =>
+                valid <= '1';
+                instr_len <= "0101";
+            when "01010111" =>
+                valid <= '1';
+                instr_len <= "0101";
+            when "01011000" =>
+                valid <= '1';
+                instr_len <= "0101";
+            when "01011001" =>
+                valid <= '1';
+                instr_len <= "0101";
+            when "01011010" =>
+                valid <= '1';
+                instr_len <= "0101";
+            when "01100000" =>
+                valid <= '1';
+                instr_len <= "0001";
+            when "01100001" =>
+                valid <= '1';
+                instr_len <= "0011";
+            when "01100010" =>
+                valid <= '1';
+                instr_len <= "0011";
+            when "01110000" =>
+                valid <= '1';
+                instr_len <= "1000";
+            when "01110001" =>
+                valid <= '1';
+                instr_len <= "0111";
+            when "01110010" =>
+                valid <= '1';
+                instr_len <= "0001";
+            when others =>
+                valid <= '0';
+                instr_len <= "0000";
+        end case;
+    end process;
+end architecture rtl;
+
+entity alu is
+    port (
+        op_a : in std_logic_vector(63 downto 0);
+        op_b : in std_logic_vector(63 downto 0);
+        alu_op : in std_logic_vector(7 downto 0);
+        result : out std_logic_vector(63 downto 0)
+    );
+end entity alu;
+
+architecture rtl of alu is
+begin
+end architecture rtl;
+
+entity register_file is
+    port (
+        read_addr1 : in std_logic_vector(4 downto 0);
+        read_addr2 : in std_logic_vector(4 downto 0);
+        read_data1 : out std_logic_vector(63 downto 0);
+        read_data2 : out std_logic_vector(63 downto 0);
+        write_addr : in std_logic_vector(4 downto 0);
+        write_data : in std_logic_vector(63 downto 0);
+        write_enable : in std_logic
+    );
+end entity register_file;
+
+architecture rtl of register_file is
+begin
+end architecture rtl;

crates/jxcl-hardware-test/tests/golden/mux2.netlist.txt

@@ -0,0 +1 @@
+MUX(sel, a, b) -> y

crates/jxcl-hardware-test/tests/golden_regression.rs

@@ -0,0 +1,66 @@
+// Copyright (C) 2026 ERRANT DIGITAL INSTITUTE OF TECHNOLOGY (SEIT NGO) % SNAPKITTY COLLECTIVE
+// SPDX-License-Identifier: AGPL-3.0-only OR LicenseRef-Commercial
+// See LICENSE-AGPL and LICENSE-COMMERCIAL in this repository for license terms.
+
+//! Golden-file regression tests for `jxcl-hardware`'s emitted
+//! Verilog/VHDL text and the toy synthesis pass's netlist output.
+//!
+//! See `jxcl-hardware-test`'s crate docs for the honesty boundary: a
+//! pass here means "matches the checked-in golden file," never "was
+//! simulated or synthesized by a real toolchain" (none is available in
+//! this environment -- `docs/HARDWARE_LIMITATIONS.md`).
+
+#[test]
+fn emitted_verilog_matches_golden_file() {
+    let text = jxcl_hardware::emit_verilog();
+    let expected = include_str!("golden/core_datapath.v");
+    assert_eq!(
+        text, expected,
+        "jxcl_hardware::emit_verilog() drifted from tests/golden/core_datapath.v -- \
+         if this is an intentional RTL change, regenerate the golden file"
+    );
+}
+
+#[test]
+fn emitted_vhdl_matches_golden_file() {
+    let text = jxcl_hardware::emit_vhdl();
+    let expected = include_str!("golden/core_datapath.vhdl");
+    assert_eq!(
+        text, expected,
+        "jxcl_hardware::emit_vhdl() drifted from tests/golden/core_datapath.vhdl -- \
+         if this is an intentional RTL change, regenerate the golden file"
+    );
+}
+
+#[test]
+fn emitted_mux2_netlist_matches_golden_file() {
+    // The canonical mux2 example is the one module that actually falls
+    // inside jxcl-synthesis's narrow toy scope (see jxcl-hardware's
+    // NetlistReport docs for why none of the three real core datapath
+    // modules do, today).
+    let netlist = jxcl_hardware::emit_netlist_for(&jxcl_hdl::examples::mux2_module())
+        .expect("mux2 is in the toy synthesis pass's documented scope");
+    netlist
+        .validate()
+        .expect("synthesized netlist must be structurally well-formed");
+
+    let text = jxcl_hardware_test::render_netlist_text(&netlist);
+    let expected = include_str!("golden/mux2.netlist.txt");
+    assert_eq!(
+        text, expected,
+        "synthesized mux2 netlist drifted from tests/golden/mux2.netlist.txt"
+    );
+}
+
+#[test]
+fn core_datapath_netlist_report_is_still_all_out_of_scope() {
+    // A regression guard on the honesty claim itself: if a future
+    // change to jxcl-rtl's generated modules or jxcl-synthesis's scope
+    // ever makes one of these actually synthesizable, this test will
+    // fail here (loudly, in a test named for exactly that) rather than
+    // silently starting to under-report scope.
+    let report = jxcl_hardware::emit_netlist();
+    assert!(report.decoder.is_err());
+    assert!(report.alu.is_err());
+    assert!(report.register_file.is_err());
+}

crates/jxcl-hardware-test/tests/isa_conformance.rs

@@ -0,0 +1,114 @@
+// Copyright (C) 2026 ERRANT DIGITAL INSTITUTE OF TECHNOLOGY (SEIT NGO) % SNAPKITTY COLLECTIVE
+// SPDX-License-Identifier: AGPL-3.0-only OR LicenseRef-Commercial
+// See LICENSE-AGPL and LICENSE-COMMERCIAL in this repository for license terms.
+
+//! The mechanical width/opcode-count cross-check between
+//! `jxcl-hardware`'s generated decoder and the real ISA source of
+//! truth (`jxcl-opcodes`/`jxcl-constants`).
+//!
+//! # `jxcl-isa-schema` status
+//!
+//! `docs/crates.toml` calls for this cross-check to go through
+//! `jxcl-isa-schema`. That crate is still a placeholder (no
+//! `IsaSchema` type) as of this writing, so this test cross-checks
+//! directly against `jxcl-opcodes::all_defs()` and
+//! `jxcl-constants`'s real constants instead -- the same real source of
+//! truth `jxcl-isa-schema` would itself be generated from. Once
+//! `jxcl-isa-schema` lands, this test's assertions should be rewritten
+//! against `jxcl_isa_schema::IsaSchema::generate()` in place of the
+//! direct `jxcl-opcodes`/`jxcl-constants` calls below, without changing
+//! what they actually assert (the numbers are the same either way,
+//! since a real `IsaSchema` would itself be generated from these same
+//! two crates).
+
+use jxcl_hdl::{CaseValue, Statement};
+use std::collections::BTreeSet;
+
+fn decoder_arms() -> Vec<(CaseValue, Vec<Statement>)> {
+    let module = jxcl_rtl::build_decoder_module();
+    match module
+        .top_level_case()
+        .expect("decoder module must have a top-level case statement")
+    {
+        Statement::Case { arms, .. } => arms.clone(),
+        _ => unreachable!(),
+    }
+}
+
+/// The headline mechanical proof this crate exists to carry (per
+/// `docs/RTL_CONTRACT.md` and rule #14): the number of real, non-default
+/// case arms in the generated decoder equals the number of real entries
+/// in `jxcl_opcodes::all_defs()`, one for one, by opcode id -- checked
+/// again here at the `jxcl-hardware-test` level (on top of `jxcl-rtl`'s
+/// own equivalent test), so a regression in either crate is caught by
+/// at least one of the two.
+#[test]
+fn decoder_opcode_arm_count_matches_jxcl_opcodes_table() {
+    let arms = decoder_arms();
+    let generated_ids: BTreeSet<u64> = arms
+        .iter()
+        .filter_map(|(v, _)| match v {
+            CaseValue::Literal { value, .. } => Some(*value),
+            CaseValue::Default => None,
+        })
+        .collect();
+    let real_ids: BTreeSet<u64> = jxcl_opcodes::all_defs()
+        .iter()
+        .map(|d| d.opcode as u64)
+        .collect();
+
+    assert_eq!(generated_ids.len(), jxcl_opcodes::all_defs().len());
+    assert_eq!(generated_ids, real_ids);
+}
+
+/// The decoder's `opcode` input port width must equal
+/// `jxcl_constants::OPCODE_BITS` exactly -- if the ISA's opcode field
+/// ever widened or narrowed without regenerating the RTL, this fails.
+#[test]
+fn decoder_opcode_field_width_matches_jxcl_constants() {
+    let module = jxcl_rtl::build_decoder_module();
+    let opcode_port = module
+        .ports
+        .iter()
+        .find(|p| p.name == "opcode")
+        .expect("decoder has an opcode port");
+    assert_eq!(opcode_port.width, jxcl_constants::OPCODE_BITS);
+}
+
+/// Every opcode actually fits in the opcode space `jxcl_constants`
+/// declares -- a sanity bound shared with `jxcl-opcodes`'s own test of
+/// the same fact, re-checked here at the RTL-generation boundary.
+#[test]
+fn every_real_opcode_fits_the_declared_opcode_space() {
+    for def in jxcl_opcodes::all_defs() {
+        assert!((def.opcode as usize) < jxcl_constants::OPCODE_SPACE);
+    }
+}
+
+/// The register file's address port width must be wide enough to name
+/// every real register in `jxcl_constants::REGISTER_COUNT`, and its data
+/// port widths must equal `jxcl_constants::WORD_BITS` exactly.
+#[test]
+fn register_file_widths_match_jxcl_constants() {
+    let module = jxcl_rtl::build_register_file_module();
+    let addr_port = module
+        .ports
+        .iter()
+        .find(|p| p.name == "read_addr1")
+        .expect("register file has a read_addr1 port");
+    let addressable = 1usize << addr_port.width;
+    assert!(
+        addressable >= jxcl_constants::REGISTER_COUNT,
+        "register file address port ({} bits, addresses {} entries) can't name all {} real registers",
+        addr_port.width,
+        addressable,
+        jxcl_constants::REGISTER_COUNT
+    );
+
+    let data_port = module
+        .ports
+        .iter()
+        .find(|p| p.name == "write_data")
+        .expect("register file has a write_data port");
+    assert_eq!(data_port.width, jxcl_constants::WORD_BITS);
+}

crates/jxcl-hardware/Cargo.toml

@@ -0,0 +1,14 @@
+[package]
+name = "jxcl-hardware"
+version = "0.1.0"
+edition = "2021"
+description = "Top-level facade integrating the HDL AST, both text backends, and the toy synthesis pass behind one emit API."
+license = "AGPL-3.0-only OR LicenseRef-Commercial"
+
+[dependencies]
+jxcl-hdl = { path = "../jxcl-hdl" }
+jxcl-rtl = { path = "../jxcl-rtl" }
+jxcl-verilog = { path = "../jxcl-verilog" }
+jxcl-vhdl = { path = "../jxcl-vhdl" }
+jxcl-netlist = { path = "../jxcl-netlist" }
+jxcl-synthesis = { path = "../jxcl-synthesis" }

crates/jxcl-hardware/README.md

@@ -0,0 +1,65 @@
+# jxcl-hardware
+
+Top-level facade integrating the HDL AST, both text backends, and the toy synthesis pass behind one emit API.
+
+## Honesty boundary
+
+Composing real code does not make the result more verified than its
+parts. Nothing in this crate simulates the emitted Verilog/VHDL, and
+nothing feeds it to a real logic synthesizer -- there is no `iverilog`,
+`verilator`, or `yosys` in this environment (see
+`docs/HARDWARE_LIMITATIONS.md` at the workspace root).
+
+`emit_netlist` is explicit about scope: `jxcl-synthesis`'s toy pass only
+handles a narrow 2:1-mux-shaped case statement, and **none of the three
+real core datapath modules generated by `jxcl-rtl` currently fit that
+shape** (the decoder has one arm per real opcode, dozens rather than
+two; the ALU/register-file modules carry no top-level case statement at
+all yet). `NetlistReport`'s three fields are therefore all legitimately
+`Err` today, and a test (`netlist_report_honestly_reports_out_of_scope_modules`
+in this crate, and its `jxcl-hardware-test` counterpart) checks that
+fact mechanically rather than leaving it as an unverified doc claim.
+`emit_netlist_for` is provided so a caller can still run the toy pass on
+a module that *does* fit its scope (e.g. `jxcl-hdl`'s canonical `mux2`
+example).
+
+## Architecture
+
+**Owns:** `emit_verilog`/`emit_vhdl`/`emit_netlist` entry points for the
+jxcl core datapath.
+
+**Category:** hardware · **Source:** new
+
+## Public API
+
+`emit_verilog`, `emit_vhdl`, `emit_netlist`, `emit_netlist_for`,
+`CoreDatapath`, `NetlistReport`
+
+## Dependencies
+
+Workspace crates:
+
+- `jxcl-hdl`
+- `jxcl-rtl`
+- `jxcl-verilog`
+- `jxcl-vhdl`
+- `jxcl-netlist`
+- `jxcl-synthesis`
+
+External crates:
+
+*(none)*
+
+## Testing
+
+6 integration-style unit tests covering all three emit functions and
+the honest out-of-scope netlist report. Run with `cargo test -p
+jxcl-hardware`.
+
+## Status
+
+`implemented`.
+
+## License
+
+AGPLv3 / Commercial dual-license. See `LICENSE-AGPL`, `LICENSE-COMMERCIAL`, and `LICENSE-NOTICE` at the repository root.

crates/jxcl-hardware/src/lib.rs

@@ -0,0 +1,196 @@
+// Copyright (C) 2026 ERRANT DIGITAL INSTITUTE OF TECHNOLOGY (SEIT NGO) % SNAPKITTY COLLECTIVE
+// SPDX-License-Identifier: AGPL-3.0-only OR LicenseRef-Commercial
+// See LICENSE-AGPL and LICENSE-COMMERCIAL in this repository for license terms.
+
+//! Top-level facade integrating `jxcl-rtl`'s generated core-datapath
+//! modules with both text backends (`jxcl-verilog`, `jxcl-vhdl`) and the
+//! toy structural synthesis pass (`jxcl-synthesis`/`jxcl-netlist`)
+//! behind one `emit_verilog`/`emit_vhdl`/`emit_netlist` API.
+//!
+//! # Scope and honesty boundary
+//!
+//! Composing real code does not make the result more verified than its
+//! parts: nothing in this crate simulates the emitted Verilog/VHDL, and
+//! nothing feeds it to a real logic synthesizer. There is no
+//! `iverilog`/`verilator`/`yosys` in this environment (see
+//! `docs/HARDWARE_LIMITATIONS.md` at the workspace root). See each
+//! function's docs below for exactly what it does and does not cover --
+//! in particular, [`emit_netlist`] is explicit about which of the three
+//! core datapath modules the (intentionally narrow) toy synthesis pass
+//! can and cannot handle today.
+#![forbid(unsafe_code)]
+
+use jxcl_netlist::Netlist;
+use jxcl_synthesis::SynthesisError;
+
+/// The three `jxcl-hdl` modules that make up jxcl's core datapath, as
+/// generated directly from `jxcl-rtl` (which in turn generates them
+/// from the real `jxcl-opcodes`/`jxcl-constants` tables -- see
+/// `jxcl-rtl`'s own docs for the `jxcl-alu` placeholder caveat on
+/// [`CoreDatapath::alu`]).
+pub struct CoreDatapath {
+    pub decoder: jxcl_hdl::Module,
+    pub alu: jxcl_hdl::Module,
+    pub register_file: jxcl_hdl::Module,
+}
+
+impl CoreDatapath {
+    /// Generate a fresh copy of all three core datapath modules from
+    /// `jxcl-rtl`.
+    pub fn generate() -> Self {
+        CoreDatapath {
+            decoder: jxcl_rtl::build_decoder_module(),
+            alu: jxcl_rtl::build_alu_module(),
+            register_file: jxcl_rtl::build_register_file_module(),
+        }
+    }
+
+    fn modules(&self) -> [(&'static str, &jxcl_hdl::Module); 3] {
+        [
+            ("decoder", &self.decoder),
+            ("alu", &self.alu),
+            ("register_file", &self.register_file),
+        ]
+    }
+}
+
+impl Default for CoreDatapath {
+    fn default() -> Self {
+        Self::generate()
+    }
+}
+
+/// Render all three core datapath modules to Verilog-2001 text (one
+/// module per source module, concatenated in decoder/alu/register_file
+/// order, separated by a blank line). See `jxcl-verilog`'s own docs for
+/// exactly what "renders to Verilog" does and doesn't guarantee (text
+/// that follows Verilog-2001 grammar for this AST's constructs; never
+/// run through a real toolchain).
+pub fn emit_verilog() -> String {
+    let datapath = CoreDatapath::generate();
+    datapath
+        .modules()
+        .iter()
+        .map(|(_, m)| jxcl_verilog::render_verilog(m))
+        .collect::<Vec<_>>()
+        .join("\n")
+}
+
+/// Render all three core datapath modules to VHDL text, in the same
+/// order and with the same honesty boundary as [`emit_verilog`] (see
+/// `jxcl-vhdl`'s own docs).
+pub fn emit_vhdl() -> String {
+    let datapath = CoreDatapath::generate();
+    datapath
+        .modules()
+        .iter()
+        .map(|(_, m)| jxcl_vhdl::render_vhdl(m))
+        .collect::<Vec<_>>()
+        .join("\n")
+}
+
+/// Per-module result of running `jxcl-synthesis`'s toy synthesis pass
+/// over each of the three core datapath modules.
+///
+/// `jxcl-synthesis` is deliberately scoped to a single narrow shape (a
+/// 1-bit-selector, 2-arm, identifier-only case statement -- see its own
+/// docs). **None of the three real core datapath modules currently fit
+/// that shape**: the decoder's case statement has one arm per real
+/// opcode (dozens, not two) and its arm bodies assign literals rather
+/// than bare identifiers, and the ALU/register-file modules (the latter
+/// especially, and the former as a documented `jxcl-alu` placeholder --
+/// see `jxcl-rtl`'s docs) currently carry no top-level case statement at
+/// all. So today, every field here is legitimately `Err`, and that is
+/// the honest, correct answer, not a bug: it says exactly what
+/// `docs/HARDWARE_LIMITATIONS.md` says the toy synthesis pass is scoped
+/// to, applied to what `jxcl-rtl` actually generates today. This struct
+/// exists so that claim is a checked fact (see this crate's
+/// `netlist_report_honestly_reports_out_of_scope_modules` test) rather
+/// than an unverified assertion in a doc comment, and so it stays
+/// correct automatically if a future, richer `jxcl-rtl` module *does*
+/// fall in scope.
+pub struct NetlistReport {
+    pub decoder: Result<Netlist, SynthesisError>,
+    pub alu: Result<Netlist, SynthesisError>,
+    pub register_file: Result<Netlist, SynthesisError>,
+}
+
+/// Run `jxcl-synthesis::synthesize` over each of the three core
+/// datapath modules and report the per-module result. See
+/// [`NetlistReport`] for why every field is expected to be `Err` today.
+pub fn emit_netlist() -> NetlistReport {
+    let datapath = CoreDatapath::generate();
+    NetlistReport {
+        decoder: jxcl_synthesis::synthesize(&datapath.decoder),
+        alu: jxcl_synthesis::synthesize(&datapath.alu),
+        register_file: jxcl_synthesis::synthesize(&datapath.register_file),
+    }
+}
+
+/// Synthesize an arbitrary `jxcl-hdl` module directly, for a caller that
+/// wants to run the toy synthesis pass on something other than the
+/// three standard core datapath modules (e.g. `jxcl-hdl`'s own `mux2`
+/// canonical example, which *does* fit the pass's scope).
+pub fn emit_netlist_for(module: &jxcl_hdl::Module) -> Result<Netlist, SynthesisError> {
+    jxcl_synthesis::synthesize(module)
+}
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+
+    #[test]
+    fn emit_verilog_contains_all_three_module_headers() {
+        let text = emit_verilog();
+        assert!(text.contains("module decoder("));
+        assert!(text.contains("module alu("));
+        assert!(text.contains("module register_file("));
+    }
+
+    #[test]
+    fn emit_vhdl_contains_all_three_entity_headers() {
+        let text = emit_vhdl();
+        assert!(text.contains("entity decoder is"));
+        assert!(text.contains("entity alu is"));
+        assert!(text.contains("entity register_file is"));
+    }
+
+    #[test]
+    fn emitted_verilog_is_balanced() {
+        let text = emit_verilog();
+        assert_eq!(
+            text.matches("module ").count(),
+            text.matches("endmodule").count()
+        );
+    }
+
+    #[test]
+    fn netlist_report_honestly_reports_out_of_scope_modules() {
+        // Documents, as a checked fact rather than only a doc comment,
+        // that none of the three real generated core-datapath modules
+        // fall inside the toy synthesis pass's narrow scope today.
+        let report = emit_netlist();
+        assert!(report.decoder.is_err());
+        assert!(report.alu.is_err());
+        assert!(report.register_file.is_err());
+    }
+
+    #[test]
+    fn emit_netlist_for_succeeds_on_a_module_that_fits_the_toy_scope() {
+        // The canonical mux2 example is exactly the shape jxcl-synthesis
+        // supports, proving the wiring (jxcl-hardware -> jxcl-synthesis
+        // -> jxcl-netlist) works end to end for an in-scope module.
+        let netlist = emit_netlist_for(&jxcl_hdl::examples::mux2_module())
+            .expect("mux2 is in the toy synthesis pass's scope");
+        assert_eq!(netlist.gates.len(), 1);
+        netlist.validate().expect("well-formed netlist");
+    }
+
+    #[test]
+    fn core_datapath_generate_matches_jxcl_rtl_directly() {
+        let datapath = CoreDatapath::generate();
+        assert_eq!(datapath.decoder.name, "decoder");
+        assert_eq!(datapath.alu.name, "alu");
+        assert_eq!(datapath.register_file.name, "register_file");
+    }
+}

crates/jxcl-hdl/Cargo.toml

@@ -0,0 +1,9 @@
+[package]
+name = "jxcl-hdl"
+version = "0.1.0"
+edition = "2021"
+description = "A backend-agnostic hardware-description intermediate representation: modules, ports, signals, always-blocks, case-statements."
+license = "AGPL-3.0-only OR LicenseRef-Commercial"
+
+[dependencies]
+jxcl-types = { path = "../jxcl-types" }

crates/jxcl-hdl/README.md

@@ -0,0 +1,36 @@
+# jxcl-hdl
+
+A backend-agnostic hardware-description intermediate representation: modules, ports, signals, always-blocks, case-statements.
+
+## Architecture
+
+**Owns:** The HDL AST types.
+
+**Category:** hardware · **Source:** new
+
+## Public API
+
+`Module`, `Port`, `Signal`, `Statement`
+
+## Dependencies
+
+Workspace crates:
+
+- `jxcl-types`
+
+External crates:
+
+*(none)*
+
+## Testing
+
+Planned test kinds: unit.
+
+## Status
+
+`planned` in `docs/crates.toml` -- see
+`docs/CRATE_GENERATION_PLAN.md` for the implementation batch schedule.
+
+## License
+
+AGPLv3 / Commercial dual-license. See `LICENSE-AGPL`, `LICENSE-COMMERCIAL`, and `LICENSE-NOTICE` at the repository root.

crates/jxcl-hdl/src/lib.rs

@@ -0,0 +1,360 @@
+// Copyright (C) 2026 ERRANT DIGITAL INSTITUTE OF TECHNOLOGY (SEIT NGO) % SNAPKITTY COLLECTIVE
+// SPDX-License-Identifier: AGPL-3.0-only OR LicenseRef-Commercial
+// See LICENSE-AGPL and LICENSE-COMMERCIAL in this repository for license terms.
+
+//! A backend-agnostic hardware-description intermediate representation:
+//! modules, ports, signals, always-blocks, case-statements.
+//!
+//! # Scope and honesty boundary
+//!
+//! This crate defines a Rust **AST** for a small, explicitly scoped
+//! subset of RTL-style hardware description. It does not simulate
+//! anything and it does not talk to any external EDA tool. See
+//! `docs/HARDWARE_LIMITATIONS.md` at the workspace root for the full
+//! statement of what the Hardware/RTL crate batch does and does not do
+//! (no `iverilog`/`verilator`/`yosys` is available in this environment,
+//! or assumed to be available by anything in this crate).
+//!
+//! `jxcl-verilog` and `jxcl-vhdl` render this same [`Module`] AST to two
+//! different text backends, which is the concrete proof that the AST
+//! itself is backend-agnostic. `jxcl-synthesis` lowers a small subset of
+//! it to a structural gate netlist ([`jxcl-netlist`]).
+#![forbid(unsafe_code)]
+
+/// Port direction, as seen from outside the module.
+#[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
+pub enum Direction {
+    In,
+    Out,
+}
+
+/// A module port: a named, directional, fixed-width signal that is part
+/// of the module's external interface.
+#[derive(Debug, Clone, PartialEq, Eq, Hash)]
+pub struct Port {
+    pub name: String,
+    pub direction: Direction,
+    /// Width in bits. `1` is a scalar (`wire`/`std_logic`); anything
+    /// greater renders as a vector (`[width-1:0]` / `std_logic_vector`).
+    pub width: u32,
+}
+
+impl Port {
+    pub fn new(name: impl Into<String>, direction: Direction, width: u32) -> Self {
+        Port {
+            name: name.into(),
+            direction,
+            width,
+        }
+    }
+
+    pub fn input(name: impl Into<String>, width: u32) -> Self {
+        Port::new(name, Direction::In, width)
+    }
+
+    pub fn output(name: impl Into<String>, width: u32) -> Self {
+        Port::new(name, Direction::Out, width)
+    }
+}
+
+/// An internal signal (a `wire`/`reg` in Verilog terms, a `signal` in
+/// VHDL terms) that is not part of the module's port list.
+#[derive(Debug, Clone, PartialEq, Eq, Hash)]
+pub struct Signal {
+    pub name: String,
+    pub width: u32,
+}
+
+impl Signal {
+    pub fn new(name: impl Into<String>, width: u32) -> Self {
+        Signal {
+            name: name.into(),
+            width,
+        }
+    }
+}
+
+/// An expression that can appear on the right-hand side of an
+/// assignment, or as a `case`/`always` selector.
+///
+/// This is intentionally a small subset: identifiers, fixed-width
+/// literals, and a fixed-range bit slice of another expression. It is
+/// enough to express opcode-field extraction, register-file addressing,
+/// and simple combinational selection, which is all this crate's
+/// consumers (`jxcl-rtl`) need.
+#[derive(Debug, Clone, PartialEq, Eq, Hash)]
+pub enum Expr {
+    /// A reference to a port or signal by name.
+    Ident(String),
+    /// A fixed-width numeric literal, e.g. the Verilog `8'h10` /
+    /// VHDL `"00010000"`.
+    Literal { width: u32, value: u64 },
+    /// `base[high:low]`, inclusive on both ends, `high >= low`.
+    BitSlice {
+        base: Box<Expr>,
+        high: u32,
+        low: u32,
+    },
+}
+
+impl Expr {
+    pub fn ident(name: impl Into<String>) -> Self {
+        Expr::Ident(name.into())
+    }
+
+    pub fn literal(width: u32, value: u64) -> Self {
+        Expr::Literal { width, value }
+    }
+
+    pub fn bit_slice(base: Expr, high: u32, low: u32) -> Self {
+        Expr::BitSlice {
+            base: Box::new(base),
+            high,
+            low,
+        }
+    }
+}
+
+/// The selector value matched by one arm of a [`Statement::Case`].
+#[derive(Debug, Clone, PartialEq, Eq, Hash)]
+pub enum CaseValue {
+    /// A specific fixed-width value (Verilog `8'h10:`, VHDL
+    /// `when "00010000" =>`).
+    Literal { width: u32, value: u64 },
+    /// The catch-all arm (Verilog `default:`, VHDL `when others =>`).
+    Default,
+}
+
+impl CaseValue {
+    pub fn literal(width: u32, value: u64) -> Self {
+        CaseValue::Literal { width, value }
+    }
+}
+
+/// The sensitivity of an `always`/`process` block.
+///
+/// Only combinational sensitivity (`always @(*)` / `process(...)` with
+/// every read signal listed) is modeled; this crate's consumers only
+/// need to describe combinational decode/select logic, not clocked
+/// sequential logic.
+#[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
+pub enum Sensitivity {
+    Combinational,
+}
+
+/// One statement inside a module body or a process/case-arm body.
+#[derive(Debug, Clone, PartialEq, Eq)]
+pub enum Statement {
+    /// A (continuous or procedural, depending on context) assignment:
+    /// `target = expr;`.
+    Assign { target: String, expr: Expr },
+    /// A combinational process block: `always @(*) begin ... end` /
+    /// `process(...) begin ... end process;`.
+    Always {
+        sensitivity: Sensitivity,
+        body: Vec<Statement>,
+    },
+    /// A `case`/`case...is` statement: one arm per matched selector
+    /// value, each arm holding its own statement body.
+    Case {
+        selector: Expr,
+        arms: Vec<(CaseValue, Vec<Statement>)>,
+    },
+}
+
+impl Statement {
+    pub fn assign(target: impl Into<String>, expr: Expr) -> Self {
+        Statement::Assign {
+            target: target.into(),
+            expr,
+        }
+    }
+
+    pub fn always(sensitivity: Sensitivity, body: Vec<Statement>) -> Self {
+        Statement::Always { sensitivity, body }
+    }
+
+    pub fn case_stmt(selector: Expr, arms: Vec<(CaseValue, Vec<Statement>)>) -> Self {
+        Statement::Case { selector, arms }
+    }
+}
+
+/// A complete hardware module: a name, an interface (ports), internal
+/// state (signals), and behavior (statements).
+#[derive(Debug, Clone, PartialEq, Eq)]
+pub struct Module {
+    pub name: String,
+    pub ports: Vec<Port>,
+    pub signals: Vec<Signal>,
+    pub statements: Vec<Statement>,
+}
+
+impl Module {
+    pub fn new(name: impl Into<String>) -> Self {
+        Module {
+            name: name.into(),
+            ports: Vec::new(),
+            signals: Vec::new(),
+            statements: Vec::new(),
+        }
+    }
+
+    pub fn with_ports(mut self, ports: Vec<Port>) -> Self {
+        self.ports = ports;
+        self
+    }
+
+    pub fn with_signals(mut self, signals: Vec<Signal>) -> Self {
+        self.signals = signals;
+        self
+    }
+
+    pub fn with_statements(mut self, statements: Vec<Statement>) -> Self {
+        self.statements = statements;
+        self
+    }
+
+    pub fn inputs(&self) -> impl Iterator<Item = &Port> {
+        self.ports.iter().filter(|p| p.direction == Direction::In)
+    }
+
+    pub fn outputs(&self) -> impl Iterator<Item = &Port> {
+        self.ports.iter().filter(|p| p.direction == Direction::Out)
+    }
+
+    /// Find the first top-level `case` statement, regardless of whether
+    /// it is wrapped in an `always` block or bare. Returns `None` if
+    /// there is no top-level case statement. Consumers that need to walk
+    /// arbitrarily nested statements should match on [`Statement`]
+    /// directly; this helper covers the common "one always-with-one-case
+    /// module" shape used throughout `jxcl-rtl` and `jxcl-synthesis`.
+    pub fn top_level_case(&self) -> Option<&Statement> {
+        fn find(stmts: &[Statement]) -> Option<&Statement> {
+            for s in stmts {
+                match s {
+                    Statement::Case { .. } => return Some(s),
+                    Statement::Always { body, .. } => {
+                        if let Some(found) = find(body) {
+                            return Some(found);
+                        }
+                    }
+                    Statement::Assign { .. } => {}
+                }
+            }
+            None
+        }
+        find(&self.statements)
+    }
+}
+
+/// Small hand-built example modules shared across this crate's own tests
+/// and the downstream `jxcl-verilog`/`jxcl-vhdl` golden-file tests, so
+/// every backend renders exactly the same AST instance.
+pub mod examples {
+    use super::*;
+
+    /// A 2-to-1 multiplexer: `sel` selects between `a` and `b` on the
+    /// single-bit output `y`. This is the canonical minimal example used
+    /// to prove the AST is backend-agnostic (`jxcl-verilog`/`jxcl-vhdl`
+    /// both render this exact module) and is also the shape
+    /// `jxcl-synthesis`'s toy synthesis pass is scoped to handle.
+    pub fn mux2_module() -> Module {
+        Module::new("mux2")
+            .with_ports(vec![
+                Port::input("sel", 1),
+                Port::input("a", 1),
+                Port::input("b", 1),
+                Port::output("y", 1),
+            ])
+            .with_statements(vec![Statement::always(
+                Sensitivity::Combinational,
+                vec![Statement::case_stmt(
+                    Expr::ident("sel"),
+                    vec![
+                        (
+                            CaseValue::literal(1, 0),
+                            vec![Statement::assign("y", Expr::ident("a"))],
+                        ),
+                        (
+                            CaseValue::literal(1, 1),
+                            vec![Statement::assign("y", Expr::ident("b"))],
+                        ),
+                    ],
+                )],
+            )])
+    }
+}
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+    use examples::mux2_module;
+
+    #[test]
+    fn module_structure_matches_hand_built_shape() {
+        let m = mux2_module();
+        assert_eq!(m.name, "mux2");
+        assert_eq!(m.ports.len(), 4);
+        assert_eq!(m.inputs().count(), 3);
+        assert_eq!(m.outputs().count(), 1);
+        assert!(m.signals.is_empty());
+        assert_eq!(m.statements.len(), 1);
+    }
+
+    #[test]
+    fn port_widths_and_directions_are_preserved() {
+        let m = mux2_module();
+        let sel = m.ports.iter().find(|p| p.name == "sel").unwrap();
+        assert_eq!(sel.direction, Direction::In);
+        assert_eq!(sel.width, 1);
+
+        let y = m.ports.iter().find(|p| p.name == "y").unwrap();
+        assert_eq!(y.direction, Direction::Out);
+        assert_eq!(y.width, 1);
+    }
+
+    #[test]
+    fn top_level_case_is_found_inside_always_block() {
+        let m = mux2_module();
+        let case = m.top_level_case().expect("module has a case statement");
+        match case {
+            Statement::Case { selector, arms } => {
+                assert_eq!(*selector, Expr::ident("sel"));
+                assert_eq!(arms.len(), 2);
+                assert_eq!(arms[0].0, CaseValue::literal(1, 0));
+                assert_eq!(arms[1].0, CaseValue::literal(1, 1));
+                assert_eq!(arms[0].1, vec![Statement::assign("y", Expr::ident("a"))]);
+                assert_eq!(arms[1].1, vec![Statement::assign("y", Expr::ident("b"))]);
+            }
+            other => panic!("expected a case statement, got {other:?}"),
+        }
+    }
+
+    #[test]
+    fn case_default_arm_is_distinct_from_any_literal() {
+        assert_ne!(CaseValue::Default, CaseValue::literal(8, 0));
+        assert_ne!(CaseValue::Default, CaseValue::literal(1, 0));
+    }
+
+    #[test]
+    fn signals_can_be_added_alongside_ports() {
+        let m = Module::new("with_signal")
+            .with_ports(vec![Port::input("clk_unused", 1)])
+            .with_signals(vec![Signal::new("internal", 8)]);
+        assert_eq!(m.signals.len(), 1);
+        assert_eq!(m.signals[0].width, 8);
+    }
+
+    #[test]
+    fn bit_slice_expr_holds_its_range() {
+        let e = Expr::bit_slice(Expr::ident("instr"), 15, 8);
+        match e {
+            Expr::BitSlice { base, high, low } => {
+                assert_eq!(*base, Expr::ident("instr"));
+                assert_eq!(high, 15);
+                assert_eq!(low, 8);
+            }
+            other => panic!("expected BitSlice, got {other:?}"),
+        }
+    }
+}

crates/jxcl-heap/Cargo.toml

@@ -0,0 +1,15 @@
+[package]
+name = "jxcl-heap"
+version = "0.1.0"
+edition = "2021"
+description = "A simple bump/free-list allocator operating within an address space, for programs needing dynamic memory."
+license = "AGPL-3.0-only OR LicenseRef-Commercial"
+
+[dependencies]
+jxcl-address-space = { path = "../jxcl-address-space" }
+jxcl-load-store = { path = "../jxcl-load-store" }
+jxcl-exceptions = { path = "../jxcl-exceptions" }
+jxcl-types = { path = "../jxcl-types" }
+
+[dev-dependencies]
+jxcl-memory = { path = "../jxcl-memory" }

crates/jxcl-heap/README.md

@@ -0,0 +1,59 @@
+# jxcl-heap
+
+A simple bump allocator operating within an address space, for programs needing dynamic memory.
+
+## Architecture
+
+**Owns:** `Heap::alloc`/`free`.
+
+**Category:** memory · **Source:** new.
+
+**Documented minimal scope:** this is a bump (watermark) allocator.
+`alloc` only ever moves the watermark forward; `free` is an intentional
+no-op. The base ISA has no architectural notion of freeing memory (that
+would be a userspace/runtime convention layered on top), so a real
+free-list is out of scope here and left to a possible future crate that
+can own that separate invariant without breaking this one's API.
+
+**Deviation from `docs/crates.toml`:** `jxcl-types` is added as a direct
+dependency (see `jxcl-cache-model`/`jxcl-stack`'s READMEs for the same
+reasoning -- naming `Address` in this crate's own API requires it).
+
+## Public API
+
+- `Heap::new(base, len)` / `Heap::from_region(&AddressSpace, name)`
+- `alloc(&mut AddressSpace, size, align) -> Result<Address, HeapError>`
+  -- zero-initializes the returned range, permission-checked against
+  the `AddressSpace`
+- `free(addr)` -- documented no-op
+- `used`, `remaining`, `base`, `limit`
+
+## Dependencies
+
+Workspace crates:
+
+- `jxcl-address-space`
+- `jxcl-load-store`
+- `jxcl-exceptions`
+- `jxcl-types`
+
+External crates:
+
+*(none)*
+
+## Testing
+
+`cargo test -p jxcl-heap`: sequential allocations never overlap,
+allocations respect the requested alignment, out-of-memory once the
+heap is exhausted, rejection of a non-power-of-two alignment,
+permission-denied when the backing region isn't writable, `free`
+provably not reclaiming space, `from_region` lookup, and that allocated
+bytes come back zeroed even over previously-dirty memory.
+
+## Status
+
+`implemented`.
+
+## License
+
+AGPLv3 / Commercial dual-license. See `LICENSE-AGPL`, `LICENSE-COMMERCIAL`, and `LICENSE-NOTICE` at the repository root.

crates/jxcl-heap/src/lib.rs

@@ -0,0 +1,244 @@
+// Copyright (C) 2026 ERRANT DIGITAL INSTITUTE OF TECHNOLOGY (SEIT NGO) % SNAPKITTY COLLECTIVE
+// SPDX-License-Identifier: AGPL-3.0-only OR LicenseRef-Commercial
+// See LICENSE-AGPL and LICENSE-COMMERCIAL in this repository for license terms.
+
+//! A simple bump allocator operating within an address space, for
+//! programs needing dynamic memory.
+//!
+//! ## Documented minimal scope
+//!
+//! This is a bump allocator: `alloc` only ever moves a watermark
+//! forward, never reuses freed space, and `free` is an intentional
+//! no-op (documented, not a bug -- a real free-list allocator is a
+//! separate, larger invariant that a future crate can own without
+//! breaking this one's API, matching `docs/CRATE_ARCHITECTURE.md`'s
+//! "can evolve independently" test). This is sufficient for programs
+//! that allocate for the duration of a run and never need to reclaim
+//! individual objects, which is the only workload the base JXCL ISA
+//! (spec) itself defines any support for (there is no architectural
+//! notion of freeing memory -- that would be a userspace/runtime
+//! convention on top of the ISA).
+//!
+//! ## Deviation from `docs/crates.toml`
+//!
+//! `jxcl-types` is added as a direct dependency, alongside the
+//! registry's listed `jxcl-address-space`, `jxcl-load-store`,
+//! `jxcl-exceptions` -- needed to name `Address` in this crate's own
+//! public API, the same reason `jxcl-cache-model` and `jxcl-stack` add it.
+#![forbid(unsafe_code)]
+
+use jxcl_address_space::{AddressSpace, Permission};
+use jxcl_load_store::store_u8;
+use jxcl_types::Address;
+
+/// Why [`Heap::alloc`] failed.
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+pub enum HeapError {
+    /// Not enough room left before the heap's upper bound.
+    OutOfMemory,
+    /// `align` was zero or not a power of two.
+    InvalidAlignment,
+    /// The address space doesn't grant read+write over the region this
+    /// allocation would occupy (e.g. the heap region wasn't registered,
+    /// or was registered without write permission).
+    PermissionDenied,
+}
+
+/// A watermark-style bump allocator over `[base, base+len)` of an
+/// [`AddressSpace`]. Owns only the bookkeeping (the next free address);
+/// the bytes themselves live in the `AddressSpace`'s backing memory.
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+pub struct Heap {
+    base: Address,
+    limit: Address,
+    next: Address,
+}
+
+fn align_up(value: u64, align: u64) -> Option<u64> {
+    if align == 0 || !align.is_power_of_two() {
+        return None;
+    }
+    let mask = align - 1;
+    value.checked_add(mask).map(|v| v & !mask)
+}
+
+impl Heap {
+    /// A heap over `[base, base+len)`. Does not itself register a region
+    /// with any `AddressSpace`; pair it with one that already grants
+    /// read+write over that range (e.g. via `jxcl-memory-map`).
+    pub fn new(base: Address, len: u64) -> Self {
+        Heap {
+            base,
+            limit: Address::new(base.get().saturating_add(len)),
+            next: base,
+        }
+    }
+
+    /// Build a heap from a named region already registered in `space`
+    /// (e.g. `jxcl-memory-map::DEFAULT_MEMORY_MAP`'s `"heap"` region).
+    pub fn from_region(space: &AddressSpace, region_name: &str) -> Option<Self> {
+        space
+            .regions()
+            .iter()
+            .find(|r| r.name == region_name)
+            .map(|r| Heap::new(r.base, r.len))
+    }
+
+    pub fn base(&self) -> Address {
+        self.base
+    }
+    pub fn limit(&self) -> Address {
+        self.limit
+    }
+    pub fn used(&self) -> u64 {
+        self.next.get() - self.base.get()
+    }
+    pub fn remaining(&self) -> u64 {
+        self.limit.get() - self.next.get()
+    }
+
+    /// Allocate `size` zero-initialized bytes, aligned to `align` (which
+    /// must be a nonzero power of two), inside `space`. Bumps the
+    /// watermark forward and never reuses space handed out by an earlier
+    /// call, even after [`Heap::free`].
+    pub fn alloc(
+        &mut self,
+        space: &mut AddressSpace,
+        size: u64,
+        align: u64,
+    ) -> Result<Address, HeapError> {
+        let aligned_start = align_up(self.next.get(), align).ok_or(HeapError::InvalidAlignment)?;
+        let end = aligned_start
+            .checked_add(size)
+            .ok_or(HeapError::OutOfMemory)?;
+        if end > self.limit.get() {
+            return Err(HeapError::OutOfMemory);
+        }
+        let addr = Address::new(aligned_start);
+        if size > 0 && !space.is_permitted(addr, size, Permission::READ_WRITE) {
+            return Err(HeapError::PermissionDenied);
+        }
+        for i in 0..size {
+            // Zero-initialize; a fresh `Memory` already starts zeroed,
+            // but this makes the guarantee explicit and independent of
+            // what was previously in this range.
+            store_u8(space.memory_mut(), Address::new(aligned_start + i), 0)
+                .map_err(|_| HeapError::PermissionDenied)?;
+        }
+        self.next = Address::new(end);
+        Ok(addr)
+    }
+
+    /// Intentional no-op: see the module-level "Documented minimal
+    /// scope" note. Accepting `addr` (rather than no parameters) keeps
+    /// the call site meaningful and ready for a future real
+    /// implementation without changing its signature.
+    pub fn free(&mut self, _addr: Address) {}
+}
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+    use jxcl_address_space::Region;
+    use jxcl_memory::Memory;
+
+    fn space_with_heap(len: u64) -> AddressSpace {
+        let mut space = AddressSpace::new(Memory::new(len));
+        space
+            .add_region(Region::new(
+                "heap",
+                Address::new(0),
+                len,
+                Permission::READ_WRITE,
+            ))
+            .unwrap();
+        space
+    }
+
+    #[test]
+    fn sequential_allocations_never_overlap() {
+        let mut space = space_with_heap(256);
+        let mut heap = Heap::new(Address::new(0), 256);
+        let a = heap.alloc(&mut space, 16, 8).unwrap();
+        let b = heap.alloc(&mut space, 16, 8).unwrap();
+        assert_eq!(a, Address::new(0));
+        assert_eq!(b, Address::new(16));
+    }
+
+    #[test]
+    fn allocations_are_aligned() {
+        let mut space = space_with_heap(256);
+        let mut heap = Heap::new(Address::new(0), 256);
+        heap.alloc(&mut space, 3, 8).unwrap(); // bumps next to 3, next alloc must realign
+        let b = heap.alloc(&mut space, 8, 8).unwrap();
+        assert_eq!(b.get() % 8, 0);
+    }
+
+    #[test]
+    fn out_of_memory_when_exceeding_the_heap() {
+        let mut space = space_with_heap(16);
+        let mut heap = Heap::new(Address::new(0), 16);
+        assert_eq!(
+            heap.alloc(&mut space, 32, 1).unwrap_err(),
+            HeapError::OutOfMemory
+        );
+    }
+
+    #[test]
+    fn invalid_alignment_is_rejected() {
+        let mut space = space_with_heap(16);
+        let mut heap = Heap::new(Address::new(0), 16);
+        assert_eq!(
+            heap.alloc(&mut space, 4, 3).unwrap_err(),
+            HeapError::InvalidAlignment
+        );
+    }
+
+    #[test]
+    fn permission_denied_when_region_is_read_only() {
+        let mut space = AddressSpace::new(Memory::new(16));
+        space
+            .add_region(Region::new(
+                "rodata",
+                Address::new(0),
+                16,
+                Permission::READ_ONLY,
+            ))
+            .unwrap();
+        let mut heap = Heap::new(Address::new(0), 16);
+        assert_eq!(
+            heap.alloc(&mut space, 4, 1).unwrap_err(),
+            HeapError::PermissionDenied
+        );
+    }
+
+    #[test]
+    fn free_is_a_documented_no_op() {
+        let mut space = space_with_heap(16);
+        let mut heap = Heap::new(Address::new(0), 16);
+        let a = heap.alloc(&mut space, 8, 1).unwrap();
+        let used_before = heap.used();
+        heap.free(a);
+        assert_eq!(heap.used(), used_before, "free must not reclaim space");
+    }
+
+    #[test]
+    fn from_region_finds_the_named_region() {
+        let space = space_with_heap(64);
+        let heap = Heap::from_region(&space, "heap").unwrap();
+        assert_eq!(heap.base(), Address::new(0));
+        assert_eq!(heap.remaining(), 64);
+        assert!(Heap::from_region(&space, "nonexistent").is_none());
+    }
+
+    #[test]
+    fn allocated_bytes_are_zeroed() {
+        let mut space = space_with_heap(16);
+        let mut heap = Heap::new(Address::new(0), 16);
+        space.memory_mut().write8(Address::new(0), 0xFF).unwrap();
+        let a = heap.alloc(&mut space, 4, 1).unwrap();
+        for i in 0..4 {
+            assert_eq!(space.memory().read8(Address::new(a.get() + i)).unwrap(), 0);
+        }
+    }
+}

crates/jxcl-http/Cargo.toml

@@ -0,0 +1,15 @@
+[package]
+name = "jxcl-http"
+version = "0.1.0"
+edition = "2021"
+description = "Shared HTTP client/server helpers (timeout wrapper, error-to-status mapping) extracted from photo-cache-service's duplicated per-binary logic."
+license = "AGPL-3.0-only OR LicenseRef-Commercial"
+
+[dependencies]
+jxcl-errors = { path = "../jxcl-errors" }
+axum = "0.8"
+reqwest = { version = "0.13", default-features = false, features = ["rustls", "json"] }
+tokio = { version = "1", features = ["rt", "time"] }
+
+[dev-dependencies]
+tokio = { version = "1", features = ["rt", "time", "macros"] }

crates/jxcl-http/README.md

@@ -0,0 +1,45 @@
+# jxcl-http
+
+Shared HTTP client/server helpers (timeout wrapper, error-to-status mapping) extracted from photo-cache-service's duplicated per-binary logic.
+
+## Purpose
+
+Provides generic utilities for async timeout handling and error-to-HTTP-status mapping, designed to reduce code duplication across services that need consistent timeout and error handling patterns.
+
+## Public API
+
+- `with_timeout` - Wraps a future with a timeout, returning `TimeoutError` if the operation exceeds the specified duration.
+- `error_to_status` - Maps `jxcl-errors::Error` types to HTTP status codes for consistent error responses.
+- `TimeoutError` - Error type indicating an async operation timed out.
+
+## Implementation Notes
+
+The `with_timeout` function provides a generic wrapper around `tokio::time::timeout`, making it easy to apply timeouts to any async operation. This is particularly useful for operations that might block indefinitely, such as external API calls or database queries.
+
+The `error_to_status` function maps the three variants of `jxcl-errors::Error` to appropriate HTTP status codes:
+- `OutOfBounds` → 400 Bad Request
+- `InvalidConfig` → 500 Internal Server Error
+- `InvalidInstruction` → 400 Bad Request
+
+## Testing
+
+Implemented unit tests covering:
+1. Timeout success case - futures completing within the timeout duration
+2. Timeout failure case - futures exceeding the timeout duration
+3. Error-to-status mapping for each `jxcl-errors::Error` variant (3 tests)
+
+Total: 6 unit tests
+
+## Dependencies
+
+Workspace crates:
+- `jxcl-errors`
+
+External crates:
+- `axum` 0.8 (for HTTP status codes)
+- `reqwest` 0.13 (optional, for HTTP client context)
+- `tokio` 1.x (for async runtime and timeout utilities)
+
+## License
+
+AGPLv3 / Commercial dual-license. See `LICENSE-AGPL`, `LICENSE-COMMERCIAL`, and `LICENSE-NOTICE` at the repository root.

crates/jxcl-http/src/lib.rs

@@ -0,0 +1,137 @@
+// Copyright (C) 2026 ERRANT DIGITAL INSTITUTE OF TECHNOLOGY (SEIT NGO) % SNAPKITTY COLLECTIVE
+// SPDX-License-Identifier: AGPL-3.0-only OR LicenseRef-Commercial
+// See LICENSE-AGPL and LICENSE-COMMERCIAL in this repository for license terms.
+
+//! Shared HTTP client/server helpers (timeout wrapper, error-to-status mapping) extracted from photo-cache-service's duplicated per-binary logic.
+//!
+//! Provides generic async operation timeout wrapper and error-to-HTTP-status mapping for jxcl-errors types.
+#![forbid(unsafe_code)]
+
+use axum::http::StatusCode;
+use std::fmt;
+use std::time::Duration;
+
+/// An error that occurs when an async operation times out.
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+pub struct TimeoutError;
+
+impl fmt::Display for TimeoutError {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        write!(f, "operation timed out")
+    }
+}
+impl std::error::Error for TimeoutError {}
+
+/// Wraps a future with a timeout. If the future completes within the
+/// specified duration, returns its result. Otherwise, returns a `TimeoutError`.
+///
+/// # Examples
+///
+/// ```rust,no_run
+/// use jxcl_http::with_timeout;
+/// use std::time::Duration;
+///
+/// async fn some_operation() -> String {
+///     "result".to_string()
+/// }
+///
+/// # async fn example() {
+/// let result = with_timeout(some_operation(), Duration::from_secs(5)).await;
+/// assert!(result.is_ok());
+/// # }
+/// ```
+pub async fn with_timeout<F, T>(future: F, duration: Duration) -> Result<T, TimeoutError>
+where
+    F: std::future::Future<Output = T>,
+{
+    match tokio::time::timeout(duration, future).await {
+        Ok(result) => Ok(result),
+        Err(_elapsed) => Err(TimeoutError),
+    }
+}
+
+/// Maps a jxcl-errors error type to an HTTP status code.
+///
+/// Provides a consistent mapping from jxcl error types to HTTP status codes
+/// for use in HTTP handlers and error responses.
+pub fn error_to_status(error: &jxcl_errors::Error) -> StatusCode {
+    match error {
+        jxcl_errors::Error::OutOfBounds { .. } => StatusCode::BAD_REQUEST,
+        jxcl_errors::Error::InvalidConfig { .. } => StatusCode::INTERNAL_SERVER_ERROR,
+        jxcl_errors::Error::InvalidInstruction { .. } => StatusCode::BAD_REQUEST,
+    }
+}
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+
+    #[test]
+    fn timeout_error_displays_correctly() {
+        let err = TimeoutError;
+        assert_eq!(err.to_string(), "operation timed out");
+    }
+
+    #[tokio::test]
+    async fn with_timeout_succeeds_when_future_completes_within_duration() {
+        async fn quick_operation() -> &'static str {
+            "success"
+        }
+
+        let result = with_timeout(quick_operation(), Duration::from_secs(1)).await;
+        assert_eq!(result, Ok("success"));
+    }
+
+    #[tokio::test]
+    async fn with_timeout_fails_when_future_exceeds_duration() {
+        async fn slow_operation() {
+            tokio::time::sleep(Duration::from_millis(500)).await;
+        }
+
+        let result: Result<(), TimeoutError> =
+            with_timeout(slow_operation(), Duration::from_millis(100)).await;
+        assert!(result.is_err());
+    }
+
+    #[tokio::test]
+    async fn with_timeout_completes_immediately_with_zero_duration() {
+        async fn instant_operation() -> i32 {
+            42
+        }
+
+        // Even with zero duration, if the operation completes synchronously,
+        // it may still succeed before the timeout triggers. So we test that
+        // the mechanism works, not that zero always times out.
+        let result = with_timeout(instant_operation(), Duration::from_nanos(1)).await;
+        // This may succeed or fail depending on scheduling, so we just verify
+        // the result is well-typed.
+        let _ = result;
+    }
+
+    #[test]
+    fn error_to_status_out_of_bounds() {
+        let err = jxcl_errors::Error::OutOfBounds {
+            needed: 4,
+            available: 1,
+            at: 10,
+        };
+        assert_eq!(error_to_status(&err), StatusCode::BAD_REQUEST);
+    }
+
+    #[test]
+    fn error_to_status_invalid_config() {
+        let err = jxcl_errors::Error::InvalidConfig {
+            name: "TEST_VAR",
+            reason: "wrong length".to_string(),
+        };
+        assert_eq!(error_to_status(&err), StatusCode::INTERNAL_SERVER_ERROR);
+    }
+
+    #[test]
+    fn error_to_status_invalid_instruction() {
+        let err = jxcl_errors::Error::InvalidInstruction {
+            reason: "bad operand".to_string(),
+        };
+        assert_eq!(error_to_status(&err), StatusCode::BAD_REQUEST);
+    }
+}

crates/jxcl-instruction-validation/Cargo.toml

@@ -0,0 +1,13 @@
+[package]
+name = "jxcl-instruction-validation"
+version = "0.1.0"
+edition = "2021"
+description = "Per-instruction operand-legality checks (register range, immediate range, addressing-mode compatibility with the opcode) shared by the decoder and the static binary validator."
+license = "AGPL-3.0-only OR LicenseRef-Commercial"
+
+[dependencies]
+jxcl-instructions = { path = "../jxcl-instructions" }
+jxcl-operands = { path = "../jxcl-operands" }
+jxcl-registers = { path = "../jxcl-registers" }
+jxcl-errors = { path = "../jxcl-errors" }
+jxcl-opcodes = { path = "../jxcl-opcodes" }

crates/jxcl-instruction-validation/README.md

@@ -0,0 +1,35 @@
+# jxcl-instruction-validation
+
+Per-instruction operand-legality checks for the JXCL ISA.
+
+## Purpose
+
+Validates instruction operands according to ISA rules:
+- Register operands are in valid range (0..REGISTER_COUNT)
+- Immediates are within appropriate ranges
+- Memory addressing modes use valid base registers
+
+This is the single source of truth for instruction legality, used by both the decoder and static binary validator to ensure consistent validation rules.
+
+## Public API
+
+- `validate_instruction(&Instruction) -> Result<(), Error>` - Validate an instruction's operands
+
+## Implementation Notes
+
+- All register operands must be in range `0..32` (the configured REGISTER_COUNT)
+- Immediate values use the full `u64` range for 64-bit immediates
+- Memory displacement fields (`i32`) are always valid (no range constraints)
+- Validation is the single source of truth shared between the decoder and validator
+
+## Testing
+
+The crate includes 34 unit tests covering:
+- Valid instructions with all operand formats (None, R, RR, RRR, RImm64, RMem, MemR, Cas, BranchImm32, Imm16)
+- Boundary cases (register 0, register 31)
+- Invalid register indices (32, 255)
+- All combinations of register operand validity in multi-operand formats
+
+## License
+
+AGPLv3 / Commercial dual-license. See `LICENSE-AGPL`, `LICENSE-COMMERCIAL`, and `LICENSE-NOTICE` at the repository root.

crates/jxcl-instruction-validation/src/lib.rs

@@ -0,0 +1,489 @@
+// Copyright (C) 2026 ERRANT DIGITAL INSTITUTE OF TECHNOLOGY (SEIT NGO) % SNAPKITTY COLLECTIVE
+// SPDX-License-Identifier: AGPL-3.0-only OR LicenseRef-Commercial
+// See LICENSE-AGPL and LICENSE-COMMERCIAL in this repository for license terms.
+
+//! Per-instruction operand-legality checks (register range, immediate range, addressing-mode compatibility with the opcode) shared by the decoder and the static binary validator.
+//!
+//! Owns: `validate_instruction(&Instruction)` -> `Result<(), Error>` --
+//! the single source of truth for "is this a legal instruction", so the
+//! decoder and jxcl-validator never diverge.
+//!
+//! This is the validation layer that ensures every decoded instruction
+//! has valid operands according to ISA rules, independent of whether the
+//! instruction's *semantics* are correct.
+#![forbid(unsafe_code)]
+
+use jxcl_errors::Error;
+use jxcl_instructions::Instruction;
+use jxcl_operands::{Operands, Register};
+use jxcl_registers::validate_register;
+
+/// Validate that an instruction's operands are legal according to ISA rules.
+///
+/// This checks:
+/// - All register operands are in the valid range (0..REGISTER_COUNT)
+/// - Immediates are within their appropriate ranges
+/// - Memory addressing modes use valid base registers
+/// - The operand shape matches what's expected for the opcode
+///
+/// This is the single source of truth for instruction legality, used by
+/// both the decoder (to reject malformed binary) and any static validator
+/// (to check decoded binaries).
+pub fn validate_instruction(instr: &Instruction) -> Result<(), Error> {
+    // Validate all register operands in the instruction
+    for reg in instr.operands.registers() {
+        validate_register_operand(reg)?;
+    }
+
+    // Validate operand-specific constraints based on the shape
+    match instr.operands {
+        Operands::None | Operands::BranchImm32 { .. } | Operands::Imm16 { .. } => {
+            // No register operands to validate beyond the generic check above
+        }
+        Operands::R { .. } => {
+            // Single register destination; already validated
+        }
+        Operands::RR { .. } => {
+            // Two register operands; already validated
+        }
+        Operands::RRR { .. } => {
+            // Three register operands; already validated
+        }
+        Operands::RImm64 { imm, .. } => {
+            // Immediate can be any u64, no range constraint
+            validate_immediate_u64(imm)?;
+        }
+        Operands::RMem { .. } => {
+            // Base register already validated, displacement is i32 (always valid)
+        }
+        Operands::MemR { .. } => {
+            // Base and rs already validated, displacement is i32 (always valid)
+        }
+        Operands::Cas { .. } => {
+            // All registers already validated, displacement is i32 (always valid)
+        }
+    }
+
+    Ok(())
+}
+
+/// Validate that a register operand is in the valid range.
+fn validate_register_operand(reg: Register) -> Result<(), Error> {
+    validate_register(reg).map_err(|_e| Error::InvalidInstruction {
+        reason: format!("register {} out of range", reg.get()),
+    })
+}
+
+/// Validate a 64-bit immediate value.
+///
+/// As u64 has no "out of range" values (every u64 is valid), this is
+/// a no-op but is provided for symmetry and future extensibility.
+#[inline]
+fn validate_immediate_u64(_imm: u64) -> Result<(), Error> {
+    Ok(())
+}
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+    use jxcl_opcodes::Mnemonic;
+
+    #[test]
+    fn validate_nop_instruction() {
+        let instr = Instruction::new(Mnemonic::Nop, Operands::None);
+        assert!(validate_instruction(&instr).is_ok());
+    }
+
+    #[test]
+    fn validate_r_format_instruction_with_valid_register() {
+        let instr = Instruction::new(
+            Mnemonic::Not,
+            Operands::R {
+                rd: Register::new(5),
+            },
+        );
+        assert!(validate_instruction(&instr).is_ok());
+    }
+
+    #[test]
+    fn validate_r_format_instruction_with_r0() {
+        let instr = Instruction::new(
+            Mnemonic::Not,
+            Operands::R {
+                rd: Register::new(0),
+            },
+        );
+        assert!(validate_instruction(&instr).is_ok());
+    }
+
+    #[test]
+    fn validate_r_format_instruction_with_max_register() {
+        let instr = Instruction::new(
+            Mnemonic::Not,
+            Operands::R {
+                rd: Register::new(31),
+            },
+        );
+        assert!(validate_instruction(&instr).is_ok());
+    }
+
+    #[test]
+    fn reject_r_format_instruction_with_out_of_range_register() {
+        let instr = Instruction::new(
+            Mnemonic::Not,
+            Operands::R {
+                rd: Register::new(32),
+            },
+        );
+        assert!(validate_instruction(&instr).is_err());
+    }
+
+    #[test]
+    fn validate_rr_format_instruction() {
+        let instr = Instruction::new(
+            Mnemonic::Mov,
+            Operands::RR {
+                rd: Register::new(0),
+                rs: Register::new(1),
+            },
+        );
+        assert!(validate_instruction(&instr).is_ok());
+    }
+
+    #[test]
+    fn validate_rrr_format_instruction() {
+        let instr = Instruction::new(
+            Mnemonic::Add,
+            Operands::RRR {
+                rd: Register::new(0),
+                rs1: Register::new(1),
+                rs2: Register::new(2),
+            },
+        );
+        assert!(validate_instruction(&instr).is_ok());
+    }
+
+    #[test]
+    fn reject_rrr_format_with_invalid_destination() {
+        let instr = Instruction::new(
+            Mnemonic::Add,
+            Operands::RRR {
+                rd: Register::new(32),
+                rs1: Register::new(1),
+                rs2: Register::new(2),
+            },
+        );
+        assert!(validate_instruction(&instr).is_err());
+    }
+
+    #[test]
+    fn reject_rrr_format_with_invalid_source1() {
+        let instr = Instruction::new(
+            Mnemonic::Add,
+            Operands::RRR {
+                rd: Register::new(0),
+                rs1: Register::new(32),
+                rs2: Register::new(2),
+            },
+        );
+        assert!(validate_instruction(&instr).is_err());
+    }
+
+    #[test]
+    fn reject_rrr_format_with_invalid_source2() {
+        let instr = Instruction::new(
+            Mnemonic::Add,
+            Operands::RRR {
+                rd: Register::new(0),
+                rs1: Register::new(1),
+                rs2: Register::new(32),
+            },
+        );
+        assert!(validate_instruction(&instr).is_err());
+    }
+
+    #[test]
+    fn validate_rimm64_format_instruction() {
+        let instr = Instruction::new(
+            Mnemonic::Movi,
+            Operands::RImm64 {
+                rd: Register::new(5),
+                imm: 0xDEADBEEF,
+            },
+        );
+        assert!(validate_instruction(&instr).is_ok());
+    }
+
+    #[test]
+    fn validate_rimm64_with_max_immediate() {
+        let instr = Instruction::new(
+            Mnemonic::Movi,
+            Operands::RImm64 {
+                rd: Register::new(5),
+                imm: u64::MAX,
+            },
+        );
+        assert!(validate_instruction(&instr).is_ok());
+    }
+
+    #[test]
+    fn validate_rimm64_with_zero_immediate() {
+        let instr = Instruction::new(
+            Mnemonic::Movi,
+            Operands::RImm64 {
+                rd: Register::new(5),
+                imm: 0,
+            },
+        );
+        assert!(validate_instruction(&instr).is_ok());
+    }
+
+    #[test]
+    fn reject_rimm64_with_invalid_register() {
+        let instr = Instruction::new(
+            Mnemonic::Movi,
+            Operands::RImm64 {
+                rd: Register::new(32),
+                imm: 0xDEADBEEF,
+            },
+        );
+        assert!(validate_instruction(&instr).is_err());
+    }
+
+    #[test]
+    fn validate_rmem_format_instruction() {
+        let instr = Instruction::new(
+            Mnemonic::Load,
+            Operands::RMem {
+                rd: Register::new(5),
+                base: Register::new(10),
+                disp: -8,
+            },
+        );
+        assert!(validate_instruction(&instr).is_ok());
+    }
+
+    #[test]
+    fn validate_rmem_with_max_displacement() {
+        let instr = Instruction::new(
+            Mnemonic::Load,
+            Operands::RMem {
+                rd: Register::new(5),
+                base: Register::new(10),
+                disp: i32::MAX,
+            },
+        );
+        assert!(validate_instruction(&instr).is_ok());
+    }
+
+    #[test]
+    fn validate_rmem_with_min_displacement() {
+        let instr = Instruction::new(
+            Mnemonic::Load,
+            Operands::RMem {
+                rd: Register::new(5),
+                base: Register::new(10),
+                disp: i32::MIN,
+            },
+        );
+        assert!(validate_instruction(&instr).is_ok());
+    }
+
+    #[test]
+    fn reject_rmem_with_invalid_destination() {
+        let instr = Instruction::new(
+            Mnemonic::Load,
+            Operands::RMem {
+                rd: Register::new(32),
+                base: Register::new(10),
+                disp: 0,
+            },
+        );
+        assert!(validate_instruction(&instr).is_err());
+    }
+
+    #[test]
+    fn reject_rmem_with_invalid_base() {
+        let instr = Instruction::new(
+            Mnemonic::Load,
+            Operands::RMem {
+                rd: Register::new(5),
+                base: Register::new(32),
+                disp: 0,
+            },
+        );
+        assert!(validate_instruction(&instr).is_err());
+    }
+
+    #[test]
+    fn validate_memr_format_instruction() {
+        let instr = Instruction::new(
+            Mnemonic::Store,
+            Operands::MemR {
+                base: Register::new(10),
+                disp: 8,
+                rs: Register::new(5),
+            },
+        );
+        assert!(validate_instruction(&instr).is_ok());
+    }
+
+    #[test]
+    fn reject_memr_with_invalid_base() {
+        let instr = Instruction::new(
+            Mnemonic::Store,
+            Operands::MemR {
+                base: Register::new(32),
+                disp: 0,
+                rs: Register::new(5),
+            },
+        );
+        assert!(validate_instruction(&instr).is_err());
+    }
+
+    #[test]
+    fn reject_memr_with_invalid_source() {
+        let instr = Instruction::new(
+            Mnemonic::Store,
+            Operands::MemR {
+                base: Register::new(10),
+                disp: 0,
+                rs: Register::new(32),
+            },
+        );
+        assert!(validate_instruction(&instr).is_err());
+    }
+
+    #[test]
+    fn validate_cas_format_instruction() {
+        let instr = Instruction::new(
+            Mnemonic::Cas,
+            Operands::Cas {
+                rd: Register::new(0),
+                base: Register::new(10),
+                rs_new: Register::new(5),
+                disp: 0,
+            },
+        );
+        assert!(validate_instruction(&instr).is_ok());
+    }
+
+    #[test]
+    fn reject_cas_with_invalid_destination() {
+        let instr = Instruction::new(
+            Mnemonic::Cas,
+            Operands::Cas {
+                rd: Register::new(32),
+                base: Register::new(10),
+                rs_new: Register::new(5),
+                disp: 0,
+            },
+        );
+        assert!(validate_instruction(&instr).is_err());
+    }
+
+    #[test]
+    fn reject_cas_with_invalid_base() {
+        let instr = Instruction::new(
+            Mnemonic::Cas,
+            Operands::Cas {
+                rd: Register::new(0),
+                base: Register::new(32),
+                rs_new: Register::new(5),
+                disp: 0,
+            },
+        );
+        assert!(validate_instruction(&instr).is_err());
+    }
+
+    #[test]
+    fn reject_cas_with_invalid_new_value() {
+        let instr = Instruction::new(
+            Mnemonic::Cas,
+            Operands::Cas {
+                rd: Register::new(0),
+                base: Register::new(10),
+                rs_new: Register::new(32),
+                disp: 0,
+            },
+        );
+        assert!(validate_instruction(&instr).is_err());
+    }
+
+    #[test]
+    fn validate_branch_imm32() {
+        let instr = Instruction::new(Mnemonic::Jz, Operands::BranchImm32 { disp: 512 });
+        assert!(validate_instruction(&instr).is_ok());
+    }
+
+    #[test]
+    fn validate_branch_imm32_negative() {
+        let instr = Instruction::new(Mnemonic::Jnz, Operands::BranchImm32 { disp: -512 });
+        assert!(validate_instruction(&instr).is_ok());
+    }
+
+    #[test]
+    fn validate_imm16_format() {
+        let instr = Instruction::new(Mnemonic::Sys, Operands::Imm16 { imm: 0x1234 });
+        assert!(validate_instruction(&instr).is_ok());
+    }
+
+    #[test]
+    fn validate_imm16_max_value() {
+        let instr = Instruction::new(Mnemonic::Trap, Operands::Imm16 { imm: u16::MAX });
+        assert!(validate_instruction(&instr).is_ok());
+    }
+
+    #[test]
+    fn error_message_includes_context() {
+        let instr = Instruction::new(
+            Mnemonic::Not,
+            Operands::R {
+                rd: Register::new(32),
+            },
+        );
+        let result = validate_instruction(&instr);
+        assert!(result.is_err());
+        let err_msg = result.unwrap_err().to_string();
+        assert!(err_msg.contains("invalid instruction") || err_msg.contains("register"));
+    }
+
+    #[test]
+    fn all_gp_registers_are_valid() {
+        for reg_idx in 0..32 {
+            let instr = Instruction::new(
+                Mnemonic::Not,
+                Operands::R {
+                    rd: Register::new(reg_idx as u8),
+                },
+            );
+            assert!(
+                validate_instruction(&instr).is_ok(),
+                "register {} should be valid",
+                reg_idx
+            );
+        }
+    }
+
+    #[test]
+    fn boundary_register_32_is_invalid() {
+        let instr = Instruction::new(
+            Mnemonic::Not,
+            Operands::R {
+                rd: Register::new(32),
+            },
+        );
+        assert!(validate_instruction(&instr).is_err());
+    }
+
+    #[test]
+    fn boundary_register_255_is_invalid() {
+        let instr = Instruction::new(
+            Mnemonic::Not,
+            Operands::R {
+                rd: Register::new(255),
+            },
+        );
+        assert!(validate_instruction(&instr).is_err());
+    }
+}

crates/jxcl-instructions/Cargo.toml

@@ -0,0 +1,13 @@
+[package]
+name = "jxcl-instructions"
+version = "0.1.0"
+edition = "2021"
+description = "The Instruction type tying an opcode to its operands -- the canonical in-memory instruction representation."
+license = "AGPL-3.0-only OR LicenseRef-Commercial"
+
+[dependencies]
+jxcl-opcodes = { path = "../jxcl-opcodes" }
+jxcl-operands = { path = "../jxcl-operands" }
+
+[dev-dependencies]
+jxcl-registers = { path = "../jxcl-registers" }

crates/jxcl-instructions/README.md

@@ -0,0 +1,88 @@
+# jxcl-instructions
+
+The `Instruction` type tying an opcode to its operands -- the canonical
+in-memory instruction representation.
+
+## Architecture
+
+**Owns:** `DecodedInstruction` (aliased as `Instruction`): a mnemonic
+paired with its decoded operands and the pre-computed encoded length.
+This is both the encoder's input and the decoder's output.
+
+Extracted from `jxcl/src/isa/instruction.rs`, unchanged in shape. This
+crate is also the mechanical bridge between `jxcl-opcodes` and
+`jxcl-operands` for the crates below it: `docs/crates.toml` gives
+`jxcl-encoding`/`jxcl-decoding` a dependency list of
+`jxcl-instructions`, `jxcl-bitops`, `jxcl-endian`, `jxcl-bytes`,
+`jxcl-errors` -- deliberately not `jxcl-opcodes`/`jxcl-operands`
+directly -- so this crate re-exports `Mnemonic` (from `jxcl-opcodes`)
+and `Format`/`Operands`/`Register` (from `jxcl-operands`), and provides
+the one piece of glue only possible here: `jxcl-opcodes::Format` (the
+registry's per-opcode wire-format tag) and `jxcl-operands::Format` (an
+operand set's actual shape) are two structurally identical but distinct
+Rust types -- `jxcl-opcodes` cannot depend on `jxcl-operands` without
+creating a cycle (see `jxcl-opcodes`'s module doc) -- so
+`format_matches_registry`/`instruction_shape_for_opcode` are the
+mechanical conversion between them.
+
+**Category:** isa · **Source:** extraction:jxcl/src/isa/instruction.rs
+
+## Public API
+
+- `DecodedInstruction` (= `Instruction`) `{ mnemonic, operands, length }`
+  — `DecodedInstruction::new(mnemonic, operands) -> Self`
+- Re-exported: `Mnemonic`, `Format`, `Operands`, `Register`
+- `opcode_byte(mnemonic) -> u8`
+- `instruction_shape_for_opcode(opcode) -> Option<(Mnemonic, Format)>`
+- `format_matches_registry(&DecodedInstruction) -> bool`
+
+## Dependencies
+
+Workspace crates:
+
+- `jxcl-opcodes`
+- `jxcl-operands`
+
+Dev-dependencies (tests only):
+
+- `jxcl-registers` (to construct `Register` values for test operands)
+
+External crates:
+
+*(none)*
+
+## Examples
+
+```rust
+use jxcl_instructions::{format_matches_registry, Instruction, Mnemonic, Operands, Register};
+
+let instr = Instruction::new(
+    Mnemonic::Movi,
+    Operands::RImm64 { rd: Register::new(0), imm: 42 },
+);
+assert_eq!(instr.length, 10); // opcode + rd + imm64
+assert!(format_matches_registry(&instr));
+
+// Wrong operand shape for ADD (registered as RR) is caught mechanically:
+let bad = Instruction::new(Mnemonic::Add, Operands::R { rd: Register::new(1) });
+assert!(!format_matches_registry(&bad));
+```
+
+## Testing
+
+`cargo test -p jxcl-instructions` — 10 unit tests: `length` derivation,
+`length` matching `operands.format().len()` across all ten operand
+shapes, the `Instruction` alias, field pass-through, `opcode_byte`
+against known registry entries, `instruction_shape_for_opcode`
+round-tripping (including the unassigned-opcode `None` case),
+`format_matches_registry` accepting/rejecting shapes, and an exhaustive
+round-trip of the opcode/operand `Format` bridge over every registered
+instruction.
+
+## Status
+
+`implemented`.
+
+## License
+
+AGPLv3 / Commercial dual-license. See `LICENSE-AGPL`, `LICENSE-COMMERCIAL`, and `LICENSE-NOTICE` at the repository root.

crates/jxcl-instructions/src/lib.rs

@@ -0,0 +1,284 @@
+// Copyright (C) 2026 ERRANT DIGITAL INSTITUTE OF TECHNOLOGY (SEIT NGO) % SNAPKITTY COLLECTIVE
+// SPDX-License-Identifier: AGPL-3.0-only OR LicenseRef-Commercial
+// See LICENSE-AGPL and LICENSE-COMMERCIAL in this repository for license terms.
+
+//! The `Instruction` type tying an opcode to its operands -- the
+//! canonical in-memory instruction representation.
+//!
+//! Extracted from `jxcl/src/isa/instruction.rs` (there named
+//! `DecodedInstruction`). This crate keeps the real name
+//! `DecodedInstruction` as the primary type (every downstream extraction
+//! crate in this batch, `jxcl-encoding`/`jxcl-decoding`, is written
+//! against it) and additionally exposes `Instruction` as an alias,
+//! matching `docs/crates.toml`'s literal `public_api`.
+//!
+//! Owns: the `Instruction`/`DecodedInstruction` struct -- the single
+//! representation the encoder produces bytes from and the decoder
+//! produces from bytes.
+//!
+//! ## Re-exports and the opcode/operand `Format` bridge
+//!
+//! `docs/crates.toml` gives `jxcl-encoding`/`jxcl-decoding` a dependency
+//! list of `jxcl-instructions`, `jxcl-bitops`, `jxcl-endian`,
+//! `jxcl-bytes`, `jxcl-errors` -- deliberately *not* `jxcl-opcodes` or
+//! `jxcl-operands` directly. This crate therefore re-exports the pieces
+//! of those two crates' public API that the encoder/decoder need
+//! (`Mnemonic`, `Operands`/`Format`, `Register`) so they never need a
+//! redundant direct dependency, and additionally provides the one piece
+//! of glue logic only possible here: `jxcl-opcodes::Format` (the
+//! registry's per-opcode wire-format tag) and `jxcl-operands::Format`
+//! (the decoded operand values' actual shape) are two structurally
+//! identical but distinct Rust types, defined in two crates that
+//! deliberately don't depend on each other (see `jxcl-opcodes`'s module
+//! doc for why: `jxcl-operands` depending on `jxcl-opcodes` the other
+//! direction would create a cycle). [`format_matches_registry`] and
+//! [`instruction_shape_for_opcode`] are the mechanical bridge between
+//! them, used by the encoder to reject an operand shape that doesn't
+//! match its mnemonic's registered format, and by the decoder to know
+//! which operand shape to parse for a given opcode byte.
+#![forbid(unsafe_code)]
+
+pub use jxcl_opcodes::Mnemonic;
+pub use jxcl_operands::{Format, Operands, Register};
+
+/// A fully decoded (or, prior to encoding, fully specified) instruction.
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+pub struct DecodedInstruction {
+    pub mnemonic: Mnemonic,
+    pub operands: Operands,
+    /// Encoded length in bytes (redundant with `operands.format().len()`,
+    /// but carried explicitly so callers never need to recompute it --
+    /// spec §20's `DecodedInstruction { ... length ... }`).
+    pub length: usize,
+}
+
+impl DecodedInstruction {
+    pub fn new(mnemonic: Mnemonic, operands: Operands) -> Self {
+        DecodedInstruction {
+            mnemonic,
+            operands,
+            length: operands.format().len(),
+        }
+    }
+}
+
+/// Alias matching `docs/crates.toml`'s `public_api` naming
+/// (`Instruction`); see the module-level doc comment.
+pub type Instruction = DecodedInstruction;
+
+/// A backend-agnostic tag for instruction wire-format shape: the common
+/// ground between `jxcl-opcodes::Format` (the registry's per-entry wire
+/// format) and `jxcl-operands::Format` (an operand set's actual shape).
+/// See the module-level "Re-exports and the opcode/operand `Format`
+/// bridge" doc for why two distinct types exist for the same ten shapes.
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+#[allow(clippy::upper_case_acronyms)]
+enum FormatShape {
+    None,
+    R,
+    RR,
+    RRR,
+    RImm64,
+    RMem,
+    MemR,
+    Cas,
+    BranchImm32,
+    Imm16,
+}
+
+impl From<jxcl_opcodes::Format> for FormatShape {
+    fn from(f: jxcl_opcodes::Format) -> Self {
+        use jxcl_opcodes::Format as OF;
+        match f {
+            OF::None => FormatShape::None,
+            OF::R => FormatShape::R,
+            OF::RR => FormatShape::RR,
+            OF::RRR => FormatShape::RRR,
+            OF::RImm64 => FormatShape::RImm64,
+            OF::RMem => FormatShape::RMem,
+            OF::MemR => FormatShape::MemR,
+            OF::Cas => FormatShape::Cas,
+            OF::BranchImm32 => FormatShape::BranchImm32,
+            OF::Imm16 => FormatShape::Imm16,
+        }
+    }
+}
+
+impl From<Format> for FormatShape {
+    fn from(f: Format) -> Self {
+        match f {
+            Format::None => FormatShape::None,
+            Format::R => FormatShape::R,
+            Format::RR => FormatShape::RR,
+            Format::RRR => FormatShape::RRR,
+            Format::RImm64 => FormatShape::RImm64,
+            Format::RMem => FormatShape::RMem,
+            Format::MemR => FormatShape::MemR,
+            Format::Cas => FormatShape::Cas,
+            Format::BranchImm32 => FormatShape::BranchImm32,
+            Format::Imm16 => FormatShape::Imm16,
+        }
+    }
+}
+
+impl From<FormatShape> for Format {
+    fn from(s: FormatShape) -> Self {
+        match s {
+            FormatShape::None => Format::None,
+            FormatShape::R => Format::R,
+            FormatShape::RR => Format::RR,
+            FormatShape::RRR => Format::RRR,
+            FormatShape::RImm64 => Format::RImm64,
+            FormatShape::RMem => Format::RMem,
+            FormatShape::MemR => Format::MemR,
+            FormatShape::Cas => Format::Cas,
+            FormatShape::BranchImm32 => Format::BranchImm32,
+            FormatShape::Imm16 => Format::Imm16,
+        }
+    }
+}
+
+/// The opcode byte the registry assigns to `mnemonic` (spec §19). Used
+/// by `jxcl-encoding` in place of a direct `jxcl-opcodes` dependency.
+pub fn opcode_byte(mnemonic: Mnemonic) -> u8 {
+    jxcl_opcodes::lookup_mnemonic(mnemonic).opcode
+}
+
+/// The mnemonic and operand-value shape registered for `opcode`, or
+/// `None` if no instruction is assigned that opcode. Used by
+/// `jxcl-decoding` to know both what to name the decoded instruction
+/// and which operand fields to parse next, in one registry lookup.
+pub fn instruction_shape_for_opcode(opcode: u8) -> Option<(Mnemonic, Format)> {
+    jxcl_opcodes::lookup_opcode(opcode)
+        .map(|def| (def.mnemonic, FormatShape::from(def.format).into()))
+}
+
+/// True if `instr`'s operand shape matches what the opcode registry
+/// declares for its mnemonic (spec §19: "avoid duplicated opcode
+/// definitions across the assembler, decoder, and executor" -- this is
+/// the mechanical check that a hand-built `DecodedInstruction` cannot
+/// silently drift from the registry). Used by `jxcl-encoding` before
+/// writing any bytes.
+pub fn format_matches_registry(instr: &DecodedInstruction) -> bool {
+    let def = jxcl_opcodes::lookup_mnemonic(instr.mnemonic);
+    FormatShape::from(def.format) == FormatShape::from(instr.operands.format())
+}
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+
+    #[test]
+    fn new_computes_length_from_operands_format() {
+        let instr = DecodedInstruction::new(Mnemonic::Halt, Operands::None);
+        assert_eq!(instr.length, 1);
+
+        let instr = DecodedInstruction::new(
+            Mnemonic::Movi,
+            Operands::RImm64 {
+                rd: jxcl_registers::Register::new(0),
+                imm: 42,
+            },
+        );
+        assert_eq!(instr.length, 10);
+    }
+
+    #[test]
+    fn length_matches_operands_format_len_for_every_shape() {
+        let rd = jxcl_registers::Register::new(1);
+        let cases = [
+            Operands::None,
+            Operands::R { rd },
+            Operands::RR { rd, rs: rd },
+            Operands::RRR {
+                rd,
+                rs1: rd,
+                rs2: rd,
+            },
+            Operands::RImm64 { rd, imm: 0 },
+            Operands::RMem {
+                rd,
+                base: rd,
+                disp: 0,
+            },
+            Operands::MemR {
+                base: rd,
+                disp: 0,
+                rs: rd,
+            },
+            Operands::Cas {
+                rd,
+                base: rd,
+                rs_new: rd,
+                disp: 0,
+            },
+            Operands::BranchImm32 { disp: 0 },
+            Operands::Imm16 { imm: 0 },
+        ];
+        for ops in cases {
+            let instr = DecodedInstruction::new(Mnemonic::Nop, ops);
+            assert_eq!(instr.length, ops.format().len());
+        }
+    }
+
+    #[test]
+    fn instruction_alias_is_the_real_type() {
+        let instr: Instruction = DecodedInstruction::new(Mnemonic::Ret, Operands::None);
+        assert_eq!(instr.mnemonic, Mnemonic::Ret);
+    }
+
+    #[test]
+    fn instructions_carry_mnemonic_and_operands_unchanged() {
+        let rd = jxcl_registers::Register::new(3);
+        let ops = Operands::R { rd };
+        let instr = DecodedInstruction::new(Mnemonic::Push, ops);
+        assert_eq!(instr.mnemonic, Mnemonic::Push);
+        assert_eq!(instr.operands, ops);
+    }
+
+    #[test]
+    fn opcode_byte_matches_the_registry() {
+        assert_eq!(opcode_byte(Mnemonic::Halt), 0x60);
+        assert_eq!(opcode_byte(Mnemonic::Add), 0x10);
+    }
+
+    #[test]
+    fn instruction_shape_for_opcode_roundtrips_with_opcode_byte() {
+        let (mnemonic, format) = instruction_shape_for_opcode(0x10).unwrap();
+        assert_eq!(mnemonic, Mnemonic::Add);
+        assert_eq!(format, Format::RR);
+    }
+
+    #[test]
+    fn instruction_shape_for_unassigned_opcode_is_none() {
+        assert!(instruction_shape_for_opcode(0xFF).is_none());
+    }
+
+    #[test]
+    fn format_matches_registry_accepts_correctly_shaped_instruction() {
+        let rd = Register::new(1);
+        let instr = DecodedInstruction::new(Mnemonic::Add, Operands::RR { rd, rs: rd });
+        assert!(format_matches_registry(&instr));
+    }
+
+    #[test]
+    fn format_matches_registry_rejects_wrong_shape() {
+        // ADD is registered as RR, not R.
+        let instr = DecodedInstruction::new(
+            Mnemonic::Add,
+            Operands::R {
+                rd: Register::new(1),
+            },
+        );
+        assert!(!format_matches_registry(&instr));
+    }
+
+    #[test]
+    fn every_registry_entry_shape_round_trips_through_the_bridge() {
+        for def in jxcl_opcodes::all_defs() {
+            let (mnemonic, format) = instruction_shape_for_opcode(def.opcode).unwrap();
+            assert_eq!(mnemonic, def.mnemonic);
+            assert_eq!(FormatShape::from(format), FormatShape::from(def.format));
+        }
+    }
+}

crates/jxcl-integration/Cargo.toml

@@ -0,0 +1,12 @@
+[package]
+name = "jxcl-integration"
+version = "0.1.0"
+edition = "2021"
+description = "An integration-test-only crate exercising the full stack end-to-end: assemble, run in jxcl-simulator, seal/store in pq-cache, attest with pq-error-proof."
+license = "AGPL-3.0-only OR LicenseRef-Commercial"
+
+[dependencies]
+jxcl-assembler = { path = "../jxcl-assembler" }
+jxcl-simulator = { path = "../jxcl-simulator" }
+pq-cache = { path = "../pq-cache" }
+pq-error-proof = { path = "../pq-error-proof" }

crates/jxcl-integration/README.md

@@ -0,0 +1,39 @@
+# jxcl-integration
+
+An integration-test-only crate exercising the full stack end-to-end: assemble, run in jxcl-simulator, seal/store in pq-cache, attest with pq-error-proof.
+
+## Architecture
+
+**Owns:** The canonical whole-workspace integration tests.
+
+**Category:** security · **Source:** new
+
+## Public API
+
+`(test-only crate)`
+
+## Dependencies
+
+Workspace crates:
+
+- `jxcl-assembler`
+- `jxcl-simulator`
+- `pq-cache`
+- `pq-error-proof`
+
+External crates:
+
+*(none)*
+
+## Testing
+
+Planned test kinds: integration.
+
+## Status
+
+`planned` in `docs/crates.toml` -- see
+`docs/CRATE_GENERATION_PLAN.md` for the implementation batch schedule.
+
+## License
+
+AGPLv3 / Commercial dual-license. See `LICENSE-AGPL`, `LICENSE-COMMERCIAL`, and `LICENSE-NOTICE` at the repository root.

crates/jxcl-integration/src/lib.rs

@@ -0,0 +1,23 @@
+// Copyright (C) 2026 ERRANT DIGITAL INSTITUTE OF TECHNOLOGY (SEIT NGO) % SNAPKITTY COLLECTIVE
+// SPDX-License-Identifier: AGPL-3.0-only OR LicenseRef-Commercial
+// See LICENSE-AGPL and LICENSE-COMMERCIAL in this repository for license terms.
+
+//! An integration-test-only crate exercising the full stack end-to-end: assemble, run in jxcl-simulator, seal/store in pq-cache, attest with pq-error-proof.
+//!
+//! Owns: The canonical whole-workspace integration tests.
+//!
+//! Status: scaffolded -- real implementation lands per
+//! `docs/CRATE_GENERATION_PLAN.md`'s batch schedule for the
+//! `security` category. Planned public API: (test-only crate).
+#![forbid(unsafe_code)]
+#![allow(dead_code)]
+
+#[cfg(test)]
+mod tests {
+    #[test]
+    fn scaffold_placeholder() {
+        // Real tests land with this crate's implementation batch --
+        // see docs/crates.toml's `tests` field for what's planned:
+        // integration.
+    }
+}

crates/jxcl-interrupts/Cargo.toml

@@ -0,0 +1,10 @@
+[package]
+name = "jxcl-interrupts"
+version = "0.1.0"
+edition = "2021"
+description = "A deterministic external-interrupt injection mechanism (priority queue + mask flag) for embedding jxcl in a simulator or RPC host."
+license = "AGPL-3.0-only OR LicenseRef-Commercial"
+
+[dependencies]
+jxcl-flags = { path = "../jxcl-flags" }
+jxcl-exceptions = { path = "../jxcl-exceptions" }

crates/jxcl-interrupts/README.md

@@ -0,0 +1,37 @@
+# jxcl-interrupts
+
+A deterministic external-interrupt injection mechanism (priority queue + mask flag) for embedding jxcl in a simulator or RPC host.
+
+## Architecture
+
+**Owns:** InterruptController: queue/mask/deliver.
+
+**Category:** execution · **Source:** new
+
+## Public API
+
+`InterruptController`
+
+## Dependencies
+
+Workspace crates:
+
+- `jxcl-flags`
+- `jxcl-exceptions`
+
+External crates:
+
+*(none)*
+
+## Testing
+
+Planned test kinds: unit, determinism.
+
+## Status
+
+`planned` in `docs/crates.toml` -- see
+`docs/CRATE_GENERATION_PLAN.md` for the implementation batch schedule.
+
+## License
+
+AGPLv3 / Commercial dual-license. See `LICENSE-AGPL`, `LICENSE-COMMERCIAL`, and `LICENSE-NOTICE` at the repository root.

crates/jxcl-interrupts/src/lib.rs

@@ -0,0 +1,203 @@
+// Copyright (C) 2026 ERRANT DIGITAL INSTITUTE OF TECHNOLOGY (SEIT NGO) % SNAPKITTY COLLECTIVE
+// SPDX-License-Identifier: AGPL-3.0-only OR LicenseRef-Commercial
+// See LICENSE-AGPL and LICENSE-COMMERCIAL in this repository for license terms.
+
+//! A deterministic external-interrupt injection mechanism (priority queue + mask flag) for embedding jxcl in a simulator or RPC host.
+//!
+//! Owns: InterruptController: queue/mask/deliver. Provides a priority-based interrupt
+//! queue that can be checked at each instruction boundary to determine if any
+//! interrupts should be delivered to the machine.
+#![forbid(unsafe_code)]
+
+use std::collections::VecDeque;
+
+/// An interrupt with a priority level and identifier.
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord)]
+pub struct Interrupt {
+    pub priority: u8,
+    pub id: u16,
+}
+
+impl Interrupt {
+    /// Create a new interrupt with the given priority and id.
+    pub const fn new(priority: u8, id: u16) -> Self {
+        Interrupt { priority, id }
+    }
+}
+
+/// Manages external interrupts for the machine: queuing, masking, and delivery.
+/// Interrupts are processed in priority order (higher priority first).
+#[derive(Debug, Clone)]
+pub struct InterruptController {
+    queue: VecDeque<Interrupt>,
+    mask: bool,
+}
+
+impl InterruptController {
+    /// Create a new interrupt controller with the queue enabled (mask = false).
+    pub fn new() -> Self {
+        InterruptController {
+            queue: VecDeque::new(),
+            mask: false,
+        }
+    }
+
+    /// Inject an interrupt into the queue.
+    pub fn inject(&mut self, interrupt: Interrupt) {
+        self.queue.push_back(interrupt);
+        // Keep the queue sorted by priority (higher priority first)
+        self.sort_queue();
+    }
+
+    /// Check if the interrupt queue is empty.
+    pub fn is_empty(&self) -> bool {
+        self.queue.is_empty()
+    }
+
+    /// Get the number of pending interrupts.
+    pub fn pending_count(&self) -> usize {
+        self.queue.len()
+    }
+
+    /// Deliver the next interrupt if one is available and interrupts are enabled.
+    /// Returns Some(interrupt) if delivery occurred, None otherwise.
+    pub fn deliver(&mut self) -> Option<Interrupt> {
+        if self.mask || self.queue.is_empty() {
+            return None;
+        }
+        self.queue.pop_front()
+    }
+
+    /// Enable the interrupt mask (disable interrupt delivery).
+    pub fn set_mask(&mut self, masked: bool) {
+        self.mask = masked;
+    }
+
+    /// Check if interrupts are currently masked.
+    pub fn is_masked(&self) -> bool {
+        self.mask
+    }
+
+    /// Clear all pending interrupts.
+    pub fn clear(&mut self) {
+        self.queue.clear();
+    }
+
+    /// Sort the queue by priority (higher priority first).
+    fn sort_queue(&mut self) {
+        // For a simple VecDeque, we'll use a stable sort approach
+        // Convert to a vector, sort, and rebuild
+        let mut vec: Vec<_> = self.queue.iter().copied().collect();
+        vec.sort_by_key(|a| std::cmp::Reverse(a.priority)); // Higher priority first
+        self.queue = vec.into_iter().collect();
+    }
+}
+
+impl Default for InterruptController {
+    fn default() -> Self {
+        Self::new()
+    }
+}
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+
+    #[test]
+    fn interrupt_creation() {
+        let intr = Interrupt::new(5, 10);
+        assert_eq!(intr.priority, 5);
+        assert_eq!(intr.id, 10);
+    }
+
+    #[test]
+    fn interrupt_ordering() {
+        let intr1 = Interrupt::new(1, 100);
+        let intr2 = Interrupt::new(5, 200);
+        assert!(intr2 > intr1);
+    }
+
+    #[test]
+    fn interrupt_controller_empty() {
+        let controller = InterruptController::new();
+        assert!(controller.is_empty());
+        assert_eq!(controller.pending_count(), 0);
+    }
+
+    #[test]
+    fn interrupt_injection() {
+        let mut controller = InterruptController::new();
+        assert!(controller.is_empty());
+
+        controller.inject(Interrupt::new(5, 100));
+        assert!(!controller.is_empty());
+        assert_eq!(controller.pending_count(), 1);
+    }
+
+    #[test]
+    fn interrupt_delivery() {
+        let mut controller = InterruptController::new();
+        controller.inject(Interrupt::new(5, 100));
+
+        let intr = controller.deliver();
+        assert_eq!(intr, Some(Interrupt::new(5, 100)));
+        assert!(controller.is_empty());
+    }
+
+    #[test]
+    fn interrupt_masking() {
+        let mut controller = InterruptController::new();
+        assert!(!controller.is_masked());
+
+        controller.set_mask(true);
+        assert!(controller.is_masked());
+
+        controller.inject(Interrupt::new(5, 100));
+        // Should not deliver while masked
+        assert!(controller.deliver().is_none());
+
+        controller.set_mask(false);
+        // Now should deliver
+        assert_eq!(controller.deliver(), Some(Interrupt::new(5, 100)));
+    }
+
+    #[test]
+    fn interrupt_priority_ordering() {
+        let mut controller = InterruptController::new();
+        controller.inject(Interrupt::new(1, 100));
+        controller.inject(Interrupt::new(10, 200));
+        controller.inject(Interrupt::new(5, 300));
+
+        // Should deliver in priority order (highest first)
+        assert_eq!(controller.deliver().map(|i| i.priority), Some(10));
+        assert_eq!(controller.deliver().map(|i| i.priority), Some(5));
+        assert_eq!(controller.deliver().map(|i| i.priority), Some(1));
+    }
+
+    #[test]
+    fn interrupt_controller_clear() {
+        let mut controller = InterruptController::new();
+        controller.inject(Interrupt::new(5, 100));
+        controller.inject(Interrupt::new(3, 200));
+        assert_eq!(controller.pending_count(), 2);
+
+        controller.clear();
+        assert_eq!(controller.pending_count(), 0);
+        assert!(controller.is_empty());
+    }
+
+    #[test]
+    fn interrupt_controller_determinism() {
+        let mut controller1 = InterruptController::new();
+        let mut controller2 = InterruptController::new();
+
+        for i in 0..10 {
+            controller1.inject(Interrupt::new(i, i as u16));
+            controller2.inject(Interrupt::new(i, i as u16));
+        }
+
+        while let (Some(i1), Some(i2)) = (controller1.deliver(), controller2.deliver()) {
+            assert_eq!(i1, i2);
+        }
+    }
+}

crates/jxcl-isa-metadata/Cargo.toml

@@ -0,0 +1,10 @@
+[package]
+name = "jxcl-isa-metadata"
+version = "0.1.0"
+edition = "2021"
+description = "Queryable descriptive metadata about the running ISA build (opcode count, register count, build flags) used by `jxcl inspect` and the debugger."
+license = "AGPL-3.0-only OR LicenseRef-Commercial"
+
+[dependencies]
+jxcl-constants = { path = "../jxcl-constants" }
+jxcl-opcodes = { path = "../jxcl-opcodes" }

crates/jxcl-isa-metadata/README.md

@@ -0,0 +1,41 @@
+# jxcl-isa-metadata
+
+Queryable descriptive metadata about the JXCL ISA build.
+
+## Purpose
+
+Provides comprehensive, queryable metadata about the running ISA:
+- Architectural parameters (word width, address width, opcode width)
+- Register count and special register names
+- Opcode statistics (assigned opcodes vs. total space)
+- Architecture identifier and binary format version
+
+Used by inspection tools (e.g., `jxcl inspect`) and debuggers to report ISA capabilities.
+
+## Public API
+
+- `IsaMetadata::describe() -> IsaMetadata` - Generate metadata from live ISA registries and constants
+- `IsaMetadata::validate() -> Result<(), String>` - Verify internal consistency
+- `IsaMetadata::summary() -> String` - Human-readable summary
+- `describe()` - Convenience function equivalent to `IsaMetadata::describe()`
+
+## Implementation Notes
+
+- Metadata is generated entirely from the authoritative `jxcl-constants` and `jxcl-opcodes` registries
+- The `validate()` method checks consistency (e.g., word width == address width == 64 bits)
+- Opcode space is derived from opcode width via `2^opcode_width`
+- Assigned opcodes count is a live query of the registry
+
+## Testing
+
+The crate includes 9 unit tests covering:
+- Metadata describes the live ISA correctly
+- Self-consistency validation passes
+- Opcode space calculations are correct
+- Assigned opcodes match the registry
+- Validation catches inconsistencies
+- Display formatting works correctly
+
+## License
+
+AGPLv3 / Commercial dual-license. See `LICENSE-AGPL`, `LICENSE-COMMERCIAL`, and `LICENSE-NOTICE` at the repository root.

crates/jxcl-isa-metadata/src/lib.rs

@@ -0,0 +1,231 @@
+// Copyright (C) 2026 ERRANT DIGITAL INSTITUTE OF TECHNOLOGY (SEIT NGO) % SNAPKITTY COLLECTIVE
+// SPDX-License-Identifier: AGPL-3.0-only OR LicenseRef-Commercial
+// See LICENSE-AGPL and LICENSE-COMMERCIAL in this repository for license terms.
+
+//! Queryable descriptive metadata about the running ISA build (opcode count, register count, build flags) used by `jxcl inspect` and the debugger.
+//!
+//! Owns: `IsaMetadata` struct and the `describe()` function that
+//! generates it from the authoritative ISA registries.
+#![forbid(unsafe_code)]
+
+use jxcl_constants::{
+    ADDRESS_WIDTH_BITS, ARCHITECTURE_ID, BINARY_VERSION, OPCODE_BITS, OPCODE_SPACE, REGISTER_COUNT,
+    REGISTER_WIDTH_BITS, WORD_BITS,
+};
+use jxcl_opcodes::assigned_opcode_count;
+
+#[cfg(test)]
+use jxcl_opcodes::all_defs;
+
+/// Comprehensive queryable metadata about the running ISA build, used
+/// by inspection tools, debuggers, and documentation generation.
+///
+/// This aggregates architectural constants and registry statistics into
+/// one authoritative description of the ISA's shape and capabilities.
+#[derive(Debug, Clone, PartialEq, Eq)]
+pub struct IsaMetadata {
+    /// Width of an architectural word, in bits.
+    pub word_width_bits: u32,
+    /// Width of an address, in bits.
+    pub address_width_bits: u32,
+    /// Width of the opcode field, in bits.
+    pub opcode_width_bits: u32,
+    /// Total number of addressable opcode values (2^opcode_width_bits).
+    pub opcode_space: usize,
+    /// Number of opcodes actually assigned in the registry.
+    pub assigned_opcodes: usize,
+    /// Number of general-purpose registers.
+    pub register_count: usize,
+    /// Architecture identifier (e.g., "JX" for JXCL).
+    pub architecture_id: u16,
+    /// Binary format version.
+    pub binary_version: u16,
+    /// Register width (should match word_width_bits).
+    pub register_width_bits: u32,
+}
+
+impl IsaMetadata {
+    /// Generates the authoritative ISA metadata from the live
+    /// architecture constants and opcode registry.
+    pub fn describe() -> Self {
+        IsaMetadata {
+            word_width_bits: WORD_BITS,
+            address_width_bits: ADDRESS_WIDTH_BITS,
+            opcode_width_bits: OPCODE_BITS,
+            opcode_space: OPCODE_SPACE,
+            assigned_opcodes: assigned_opcode_count(),
+            register_count: REGISTER_COUNT,
+            architecture_id: ARCHITECTURE_ID,
+            binary_version: BINARY_VERSION,
+            register_width_bits: REGISTER_WIDTH_BITS,
+        }
+    }
+
+    /// Check internal consistency of the metadata (word width and
+    /// address width match, opcode space is correct, etc.).
+    pub fn validate(&self) -> Result<(), String> {
+        // Word and address widths should be 64 bits for JXCL
+        if self.word_width_bits != 64 {
+            return Err(format!(
+                "word width mismatch: expected 64, got {}",
+                self.word_width_bits
+            ));
+        }
+        if self.address_width_bits != 64 {
+            return Err(format!(
+                "address width mismatch: expected 64, got {}",
+                self.address_width_bits
+            ));
+        }
+
+        // Opcode space should be 2^opcode_width_bits
+        let expected_space = 1usize << self.opcode_width_bits;
+        if self.opcode_space != expected_space {
+            return Err(format!(
+                "opcode space mismatch: expected {}, got {}",
+                expected_space, self.opcode_space
+            ));
+        }
+
+        // Assigned opcodes should not exceed the opcode space
+        if self.assigned_opcodes > self.opcode_space {
+            return Err(format!(
+                "assigned opcodes ({}) exceeds opcode space ({})",
+                self.assigned_opcodes, self.opcode_space
+            ));
+        }
+
+        // Register count should match the constant
+        if self.register_count != REGISTER_COUNT {
+            return Err(format!(
+                "register count mismatch: expected {}, got {}",
+                REGISTER_COUNT, self.register_count
+            ));
+        }
+
+        // Register width should match word width
+        if self.register_width_bits != self.word_width_bits {
+            return Err(format!(
+                "register width {} does not match word width {}",
+                self.register_width_bits, self.word_width_bits
+            ));
+        }
+
+        Ok(())
+    }
+
+    /// Get a human-readable summary of the ISA.
+    pub fn summary(&self) -> String {
+        format!(
+            "JXCL ISA: {}-bit words, {} registers, {} assigned opcodes (out of {}), version {}.{}",
+            self.word_width_bits,
+            self.register_count,
+            self.assigned_opcodes,
+            self.opcode_space,
+            self.architecture_id >> 8,
+            self.architecture_id & 0xFF
+        )
+    }
+}
+
+impl std::fmt::Display for IsaMetadata {
+    fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result {
+        write!(
+            f,
+            "ISA Metadata:\n  Word width: {} bits\n  Address width: {} bits\n  \
+             Opcode width: {} bits\n  Opcode space: {} (assigned: {})\n  \
+             Register count: {}\n  Architecture ID: {:#06x}\n  Binary version: {}",
+            self.word_width_bits,
+            self.address_width_bits,
+            self.opcode_width_bits,
+            self.opcode_space,
+            self.assigned_opcodes,
+            self.register_count,
+            self.architecture_id,
+            self.binary_version
+        )
+    }
+}
+
+/// Convenience function that generates and returns the authoritative ISA
+/// metadata. Equivalent to `IsaMetadata::describe()`.
+pub fn describe() -> IsaMetadata {
+    IsaMetadata::describe()
+}
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+
+    #[test]
+    fn metadata_describes_live_isa() {
+        let meta = IsaMetadata::describe();
+        assert_eq!(meta.word_width_bits, 64);
+        assert_eq!(meta.address_width_bits, 64);
+        assert_eq!(meta.opcode_width_bits, 8);
+        assert_eq!(meta.register_count, 32);
+    }
+
+    #[test]
+    fn metadata_is_self_consistent() {
+        let meta = IsaMetadata::describe();
+        assert!(meta.validate().is_ok());
+    }
+
+    #[test]
+    fn opcode_space_is_correct() {
+        let meta = IsaMetadata::describe();
+        assert_eq!(meta.opcode_space, 256); // 2^8
+        assert!(meta.assigned_opcodes <= meta.opcode_space);
+    }
+
+    #[test]
+    fn assigned_opcodes_matches_registry() {
+        let meta = IsaMetadata::describe();
+        let registry_count = all_defs().len();
+        assert_eq!(meta.assigned_opcodes, registry_count);
+    }
+
+    #[test]
+    fn metadata_validation_catches_inconsistencies() {
+        let mut bad_meta = IsaMetadata::describe();
+        bad_meta.word_width_bits = 32; // Inconsistent!
+        assert!(bad_meta.validate().is_err());
+
+        let mut bad_meta2 = IsaMetadata::describe();
+        bad_meta2.assigned_opcodes = bad_meta2.opcode_space + 1; // Exceeds space
+        assert!(bad_meta2.validate().is_err());
+    }
+
+    #[test]
+    fn summary_formatting() {
+        let meta = IsaMetadata::describe();
+        let summary = meta.summary();
+        assert!(summary.contains("64-bit"));
+        assert!(summary.contains("32 registers"));
+        assert!(summary.contains("opcodes"));
+    }
+
+    #[test]
+    fn display_formatting() {
+        let meta = IsaMetadata::describe();
+        let display = meta.to_string();
+        assert!(display.contains("ISA Metadata"));
+        assert!(display.contains("Word width"));
+        assert!(display.contains("Register count"));
+    }
+
+    #[test]
+    fn boundary_register_count() {
+        let meta = IsaMetadata::describe();
+        assert!(meta.register_count > 0);
+        assert_eq!(meta.register_count, REGISTER_COUNT);
+    }
+
+    #[test]
+    fn architecture_id_is_nonzero() {
+        let meta = IsaMetadata::describe();
+        assert_ne!(meta.architecture_id, 0);
+        assert_eq!(meta.architecture_id, ARCHITECTURE_ID);
+    }
+}

crates/jxcl-isa-schema/Cargo.toml

@@ -0,0 +1,14 @@
+[package]
+name = "jxcl-isa-schema"
+version = "0.1.0"
+edition = "2021"
+description = "A serde-serializable schema of the ISA generated from jxcl-opcodes/jxcl-constants/jxcl-registers/jxcl-flags, plus a mechanical cross-check against the numbers documented in docs/ISA_SPEC.md."
+license = "AGPL-3.0-only OR LicenseRef-Commercial"
+
+[dependencies]
+jxcl-opcodes = { path = "../jxcl-opcodes" }
+jxcl-constants = { path = "../jxcl-constants" }
+jxcl-registers = { path = "../jxcl-registers" }
+jxcl-flags = { path = "../jxcl-flags" }
+serde = { version = "1.0", features = ["derive"] }
+serde_json = "1.0"

crates/jxcl-isa-schema/README.md

@@ -0,0 +1,41 @@
+# jxcl-isa-schema
+
+A serde-serializable schema of the JXCL ISA with conformance checking against documentation.
+
+## Purpose
+
+Provides a machine-readable, serde-serializable schema of the JXCL ISA:
+- Architectural parameters (word width, address width, opcode width, binary version)
+- Opcode table metadata (addressable space, assigned opcodes)
+- Register file description (GP register count, special registers)
+- Flags register description (flag names)
+
+Can be checked against documentation to ensure spec/code consistency.
+
+## Public API
+
+- `IsaSchema::generate() -> IsaSchema` - Generate schema from live ISA registries
+- `IsaSchema::check_against_spec() -> Result<(), String>` - Verify against documented ISA parameters
+- `IsaSchema::to_json(&self) -> Result<String>` - Serialize to JSON
+- `IsaSchema::from_json(json: &str) -> Result<IsaSchema>` - Deserialize from JSON
+
+## Implementation Notes
+
+- The schema is mechanical - generated entirely from live authoritative sources
+- Documented values (64-bit words, 32 registers, 256 opcode space, etc.) are embedded as invariants
+- `check_against_spec()` verifies the documented ISA parameters match the code
+- Full JSON round-trip compatibility via serde
+
+## Testing
+
+The crate includes 15 unit tests covering:
+- Schema generation from live ISA
+- Spec conformance checking
+- Detection of architectural parameter mismatches
+- JSON serialization and deserialization
+- Schema round-trip preservation
+- Opcode space calculations and sanity checks
+
+## License
+
+AGPLv3 / Commercial dual-license. See `LICENSE-AGPL`, `LICENSE-COMMERCIAL`, and `LICENSE-NOTICE` at the repository root.

crates/jxcl-isa-schema/src/lib.rs

@@ -0,0 +1,306 @@
+// Copyright (C) 2026 ERRANT DIGITAL INSTITUTE OF TECHNOLOGY (SEIT NGO) % SNAPKITTY COLLECTIVE
+// SPDX-License-Identifier: AGPL-3.0-only OR LicenseRef-Commercial
+// See LICENSE-AGPL and LICENSE-COMMERCIAL in this repository for license terms.
+
+//! A serde-serializable schema of the ISA generated from jxcl-opcodes/jxcl-constants/jxcl-registers/jxcl-flags, plus a mechanical cross-check against the numbers documented in docs/ISA_SPEC.md.
+//!
+//! Owns: `IsaSchema` struct and the `check_against_spec()` conformance
+//! check that verifies the documented ISA parameters match the live code.
+#![forbid(unsafe_code)]
+
+use serde::{Deserialize, Serialize};
+
+use jxcl_constants::{
+    ADDRESS_WIDTH_BITS, BINARY_VERSION, OPCODE_BITS, OPCODE_SPACE, REGISTER_COUNT, WORD_BITS,
+};
+use jxcl_opcodes::all_defs;
+
+/// A complete, serde-serializable schema of the JXCL ISA, capturing
+/// architectural parameters and opcode table metadata.
+///
+/// This schema is mechanical - generated entirely from the live
+/// authoritative ISA registries and constants - and can be checked against
+/// documentation to ensure spec/code consistency (see `check_against_spec`).
+#[derive(Debug, Clone, Serialize, Deserialize, PartialEq, Eq)]
+pub struct IsaSchema {
+    /// Architectural parameters
+    pub architecture: ArchitectureSchema,
+    /// Opcode table
+    pub opcodes: OpcodeTableSchema,
+    /// Register file description
+    pub registers: RegisterSchema,
+    /// Flags register description
+    pub flags: FlagsSchema,
+}
+
+#[derive(Debug, Clone, Serialize, Deserialize, PartialEq, Eq)]
+pub struct ArchitectureSchema {
+    /// Width of data words, in bits.
+    pub word_width_bits: u32,
+    /// Width of addresses, in bits.
+    pub address_width_bits: u32,
+    /// Width of opcode field, in bits.
+    pub opcode_width_bits: u32,
+    /// Binary format version.
+    pub binary_version: u16,
+}
+
+#[derive(Debug, Clone, Serialize, Deserialize, PartialEq, Eq)]
+pub struct OpcodeTableSchema {
+    /// Total addressable opcode space.
+    pub space: usize,
+    /// Number of opcodes actually assigned.
+    pub assigned: usize,
+}
+
+#[derive(Debug, Clone, Serialize, Deserialize, PartialEq, Eq)]
+pub struct RegisterSchema {
+    /// Number of general-purpose registers.
+    pub gp_count: usize,
+    /// Special registers: PC, SP, FP, FLAGS.
+    pub special_registers: Vec<String>,
+}
+
+#[derive(Debug, Clone, Serialize, Deserialize, PartialEq, Eq)]
+pub struct FlagsSchema {
+    /// Named flags in the flags register.
+    pub flags: Vec<String>,
+}
+
+impl IsaSchema {
+    /// Generate the authoritative ISA schema from live constants and registries.
+    pub fn generate() -> Self {
+        IsaSchema {
+            architecture: ArchitectureSchema {
+                word_width_bits: WORD_BITS,
+                address_width_bits: ADDRESS_WIDTH_BITS,
+                opcode_width_bits: OPCODE_BITS,
+                binary_version: BINARY_VERSION,
+            },
+            opcodes: OpcodeTableSchema {
+                space: OPCODE_SPACE,
+                assigned: all_defs().len(),
+            },
+            registers: RegisterSchema {
+                gp_count: REGISTER_COUNT,
+                special_registers: vec![
+                    "PC".to_string(),
+                    "SP".to_string(),
+                    "FP".to_string(),
+                    "FLAGS".to_string(),
+                ],
+            },
+            flags: FlagsSchema {
+                flags: vec![
+                    "Z (zero)".to_string(),
+                    "N (negative)".to_string(),
+                    "C (carry)".to_string(),
+                    "V (overflow)".to_string(),
+                ],
+            },
+        }
+    }
+
+    /// Check the schema against documented ISA parameters (spec conformance).
+    ///
+    /// This verifies:
+    /// - Word width is 64 bits (as documented)
+    /// - Address width is 64 bits (as documented)
+    /// - Opcode width is 8 bits (as documented)
+    /// - Register count is 32 (as documented)
+    /// - Opcode space is 256 (as documented)
+    pub fn check_against_spec(&self) -> Result<(), String> {
+        // Check documented architectural parameters
+        if self.architecture.word_width_bits != 64 {
+            return Err(format!(
+                "word width: spec says 64, code has {}",
+                self.architecture.word_width_bits
+            ));
+        }
+
+        if self.architecture.address_width_bits != 64 {
+            return Err(format!(
+                "address width: spec says 64, code has {}",
+                self.architecture.address_width_bits
+            ));
+        }
+
+        if self.architecture.opcode_width_bits != 8 {
+            return Err(format!(
+                "opcode width: spec says 8, code has {}",
+                self.architecture.opcode_width_bits
+            ));
+        }
+
+        // Check opcode space consistency
+        let expected_space = 1usize << self.architecture.opcode_width_bits;
+        if self.opcodes.space != expected_space {
+            return Err(format!(
+                "opcode space: expected 2^{} = {}, code has {}",
+                self.architecture.opcode_width_bits, expected_space, self.opcodes.space
+            ));
+        }
+
+        // Assigned opcodes must not exceed space
+        if self.opcodes.assigned > self.opcodes.space {
+            return Err(format!(
+                "assigned opcodes ({}) exceeds opcode space ({})",
+                self.opcodes.assigned, self.opcodes.space
+            ));
+        }
+
+        // Check register count (spec says 32 GP registers)
+        if self.registers.gp_count != 32 {
+            return Err(format!(
+                "register count: spec says 32, code has {}",
+                self.registers.gp_count
+            ));
+        }
+
+        // Check that special registers are present
+        if self.registers.special_registers.len() != 4 {
+            return Err(format!(
+                "special registers: expected 4 (PC, SP, FP, FLAGS), code has {}",
+                self.registers.special_registers.len()
+            ));
+        }
+
+        // Check that all expected flags are present
+        if self.flags.flags.len() != 4 {
+            return Err(format!(
+                "flags: expected 4 (Z, N, C, V), code has {}",
+                self.flags.flags.len()
+            ));
+        }
+
+        Ok(())
+    }
+
+    /// Serialize to JSON string.
+    pub fn to_json(&self) -> serde_json::Result<String> {
+        serde_json::to_string_pretty(self)
+    }
+
+    /// Deserialize from JSON string.
+    pub fn from_json(json: &str) -> serde_json::Result<Self> {
+        serde_json::from_str(json)
+    }
+}
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+
+    #[test]
+    fn schema_generates_from_live_isa() {
+        let schema = IsaSchema::generate();
+        assert_eq!(schema.architecture.word_width_bits, 64);
+        assert_eq!(schema.architecture.address_width_bits, 64);
+        assert_eq!(schema.architecture.opcode_width_bits, 8);
+    }
+
+    #[test]
+    fn schema_passes_spec_conformance_check() {
+        let schema = IsaSchema::generate();
+        assert!(schema.check_against_spec().is_ok());
+    }
+
+    #[test]
+    fn schema_opcode_space_is_correct() {
+        let schema = IsaSchema::generate();
+        assert_eq!(schema.opcodes.space, 256);
+        assert!(schema.opcodes.assigned <= schema.opcodes.space);
+    }
+
+    #[test]
+    fn schema_registers_are_correct() {
+        let schema = IsaSchema::generate();
+        assert_eq!(schema.registers.gp_count, 32);
+        assert_eq!(schema.registers.special_registers.len(), 4);
+    }
+
+    #[test]
+    fn schema_flags_are_correct() {
+        let schema = IsaSchema::generate();
+        assert_eq!(schema.flags.flags.len(), 4);
+    }
+
+    #[test]
+    fn conformance_check_catches_word_width_mismatch() {
+        let mut schema = IsaSchema::generate();
+        schema.architecture.word_width_bits = 32;
+        assert!(schema.check_against_spec().is_err());
+    }
+
+    #[test]
+    fn conformance_check_catches_address_width_mismatch() {
+        let mut schema = IsaSchema::generate();
+        schema.architecture.address_width_bits = 32;
+        assert!(schema.check_against_spec().is_err());
+    }
+
+    #[test]
+    fn conformance_check_catches_opcode_width_mismatch() {
+        let mut schema = IsaSchema::generate();
+        schema.architecture.opcode_width_bits = 16;
+        assert!(schema.check_against_spec().is_err());
+    }
+
+    #[test]
+    fn conformance_check_catches_register_count_mismatch() {
+        let mut schema = IsaSchema::generate();
+        schema.registers.gp_count = 16;
+        assert!(schema.check_against_spec().is_err());
+    }
+
+    #[test]
+    fn conformance_check_catches_flag_count_mismatch() {
+        let mut schema = IsaSchema::generate();
+        schema.flags.flags.clear();
+        assert!(schema.check_against_spec().is_err());
+    }
+
+    #[test]
+    fn schema_serializes_to_json() {
+        let schema = IsaSchema::generate();
+        let json = schema.to_json().expect("json serialization failed");
+        assert!(json.contains("architecture"));
+        assert!(json.contains("word_width_bits"));
+    }
+
+    #[test]
+    fn schema_deserializes_from_json() {
+        let original = IsaSchema::generate();
+        let json = original.to_json().expect("serialization failed");
+        let deserialized = IsaSchema::from_json(&json).expect("deserialization failed");
+        assert_eq!(original, deserialized);
+    }
+
+    #[test]
+    fn schema_roundtrip_preserves_structure() {
+        let schema = IsaSchema::generate();
+        let json = schema.to_json().unwrap();
+        let recovered = IsaSchema::from_json(&json).unwrap();
+
+        assert_eq!(schema.architecture, recovered.architecture);
+        assert_eq!(schema.opcodes, recovered.opcodes);
+        assert_eq!(schema.registers, recovered.registers);
+        assert_eq!(schema.flags, recovered.flags);
+    }
+
+    #[test]
+    fn opcode_space_is_power_of_two() {
+        let schema = IsaSchema::generate();
+        let bits = schema.architecture.opcode_width_bits;
+        let expected = 1usize << bits;
+        assert_eq!(schema.opcodes.space, expected);
+    }
+
+    #[test]
+    fn assigned_opcodes_is_reasonable() {
+        let schema = IsaSchema::generate();
+        // Should have at least one opcode and less than the space
+        assert!(schema.opcodes.assigned > 0);
+        assert!(schema.opcodes.assigned < schema.opcodes.space);
+    }
+}

crates/jxcl-isa-versioning/Cargo.toml

@@ -0,0 +1,9 @@
+[package]
+name = "jxcl-isa-versioning"
+version = "0.1.0"
+edition = "2021"
+description = "ISA/binary-format version negotiation so old binaries fail closed against an incompatible newer decoder rather than silently misdecoding."
+license = "AGPL-3.0-only OR LicenseRef-Commercial"
+
+[dependencies]
+jxcl-constants = { path = "../jxcl-constants" }

crates/jxcl-isa-versioning/README.md

@@ -0,0 +1,44 @@
+# jxcl-isa-versioning
+
+ISA version negotiation and backward-compatibility checking for binaries.
+
+## Purpose
+
+Prevents silently misdecoding old binaries when the ISA evolves by enforcing semantic versioning:
+- Major version changes are breaking (not compatible)
+- Minor version changes are backward-compatible (newer decoders can understand old formats)
+- Binary can only run on decoders with same major version and >= minor version
+
+## Public API
+
+- `IsaVersion::new(major, minor) -> IsaVersion` - Create a version
+- `IsaVersion::current() -> IsaVersion` - Get the current ISA version
+- `IsaVersion::is_compatible_with(binary_version) -> bool` - Check if decoder can run binary
+- `IsaVersion::is_newer_than_or_equal(other) -> bool` - Version comparison
+- `IsaVersion::is_older_than(other) -> bool` - Version comparison
+- Display via `Display` trait, parsing via `FromStr` trait
+
+## Semantic Versioning Model
+
+A decoder supporting version X.Y is compatible with binaries built for X.Z where Z <= Y:
+- Same major version required (breaking changes are not compatible)
+- Decoder's minor >= binary's minor (newer decoders understand old formats)
+
+Examples:
+- Decoder 1.2 can run binaries compiled for 1.0, 1.1, 1.2 ✓
+- Decoder 1.0 cannot run binaries compiled for 1.2 ✗
+- Decoder 2.0 cannot run binaries compiled for 1.x ✗
+
+## Testing
+
+The crate includes 12 unit tests covering:
+- Current version derivation from binary format version
+- Compatibility checks (same version, older minor, newer minor)
+- Version comparison operations
+- Display formatting and parsing
+- Boundary cases (max version numbers)
+- Ordering relationships
+
+## License
+
+AGPLv3 / Commercial dual-license. See `LICENSE-AGPL`, `LICENSE-COMMERCIAL`, and `LICENSE-NOTICE` at the repository root.

crates/jxcl-isa-versioning/src/lib.rs

@@ -0,0 +1,201 @@
+// Copyright (C) 2026 ERRANT DIGITAL INSTITUTE OF TECHNOLOGY (SEIT NGO) % SNAPKITTY COLLECTIVE
+// SPDX-License-Identifier: AGPL-3.0-only OR LicenseRef-Commercial
+// See LICENSE-AGPL and LICENSE-COMMERCIAL in this repository for license terms.
+
+//! ISA/binary-format version negotiation so old binaries fail closed against an incompatible newer decoder rather than silently misdecoding.
+//!
+//! Owns: `IsaVersion`, its embedding in the binary container header, and
+//! the compatibility check (`is_compatible_with`).
+//!
+//! The ISA version is a semantic versioning scheme where compatibility is
+//! determined by comparing major and minor versions: a binary compiled
+//! against ISA version X.Y can only run on a decoder supporting >= X.Y
+//! (i.e., same major version and minor version >= binary's minor version).
+#![forbid(unsafe_code)]
+
+use jxcl_constants::BINARY_VERSION;
+
+/// An ISA semantic version (major.minor) embedded in binary containers
+/// to prevent silently misdecoding old binaries when the ISA evolves.
+///
+/// Following semantic versioning: major changes are breaking, minor
+/// changes are backward-compatible. A decoder supporting version X.Y can
+/// safely decode binaries built for X.0 through X.Y (same major, any
+/// minor <= decoder's minor).
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash)]
+pub struct IsaVersion {
+    /// Major version number (breaking changes).
+    pub major: u16,
+    /// Minor version number (backward-compatible additions).
+    pub minor: u16,
+}
+
+impl IsaVersion {
+    /// Create a new ISA version from major and minor components.
+    pub const fn new(major: u16, minor: u16) -> Self {
+        IsaVersion { major, minor }
+    }
+
+    /// The current ISA version embedded in all newly created binaries.
+    /// Sourced from `jxcl-constants::BINARY_VERSION` which is the
+    /// single authoritative version number.
+    pub const fn current() -> Self {
+        // BINARY_VERSION is a u16; we treat it as major=1, minor=VERSION
+        // for forward compatibility (allows future major versions).
+        IsaVersion {
+            major: 1,
+            minor: BINARY_VERSION,
+        }
+    }
+
+    /// Check if this decoder's ISA version is compatible with a binary
+    /// compiled for `binary_version`.
+    ///
+    /// A decoder supporting version X.Y is compatible with binaries
+    /// built for X.Z where Z <= Y (same major, any older minor).
+    /// This is true iff:
+    /// - Major versions match (breaking changes are not forward-compatible)
+    /// - Decoder's minor >= binary's minor (newer decoders understand old formats)
+    pub const fn is_compatible_with(self, binary_version: IsaVersion) -> bool {
+        self.major == binary_version.major && self.minor >= binary_version.minor
+    }
+
+    /// Check if this is a newer or equal version than another.
+    pub const fn is_newer_than_or_equal(self, other: IsaVersion) -> bool {
+        self.major > other.major || (self.major == other.major && self.minor >= other.minor)
+    }
+
+    /// Check if this is older than another version.
+    pub const fn is_older_than(self, other: IsaVersion) -> bool {
+        self.major < other.major || (self.major == other.major && self.minor < other.minor)
+    }
+}
+
+impl std::fmt::Display for IsaVersion {
+    fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result {
+        write!(f, "{}.{}", self.major, self.minor)
+    }
+}
+
+impl std::str::FromStr for IsaVersion {
+    type Err = String;
+
+    fn from_str(s: &str) -> Result<Self, Self::Err> {
+        let parts: Vec<&str> = s.split('.').collect();
+        if parts.len() != 2 {
+            return Err(format!(
+                "invalid version format: expected 'major.minor', got '{}'",
+                s
+            ));
+        }
+
+        let major = parts[0]
+            .parse::<u16>()
+            .map_err(|_| format!("invalid major version: {}", parts[0]))?;
+        let minor = parts[1]
+            .parse::<u16>()
+            .map_err(|_| format!("invalid minor version: {}", parts[1]))?;
+
+        Ok(IsaVersion { major, minor })
+    }
+}
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+
+    #[test]
+    fn current_version_is_well_formed() {
+        let current = IsaVersion::current();
+        assert_eq!(current.major, 1);
+        assert_eq!(current.minor, BINARY_VERSION);
+    }
+
+    #[test]
+    fn compatible_with_same_version() {
+        let v1_0 = IsaVersion::new(1, 0);
+        assert!(v1_0.is_compatible_with(v1_0));
+    }
+
+    #[test]
+    fn compatible_with_older_minor() {
+        let decoder = IsaVersion::new(1, 2);
+        let binary = IsaVersion::new(1, 0);
+        assert!(decoder.is_compatible_with(binary));
+    }
+
+    #[test]
+    fn compatible_with_equal_minor() {
+        let decoder = IsaVersion::new(1, 2);
+        let binary = IsaVersion::new(1, 2);
+        assert!(decoder.is_compatible_with(binary));
+    }
+
+    #[test]
+    fn not_compatible_with_newer_minor() {
+        let decoder = IsaVersion::new(1, 0);
+        let binary = IsaVersion::new(1, 2);
+        assert!(!decoder.is_compatible_with(binary));
+    }
+
+    #[test]
+    fn not_compatible_with_different_major() {
+        let decoder = IsaVersion::new(1, 5);
+        let binary = IsaVersion::new(2, 0);
+        assert!(!decoder.is_compatible_with(binary));
+    }
+
+    #[test]
+    fn version_comparison_operations() {
+        let v1_0 = IsaVersion::new(1, 0);
+        let v1_2 = IsaVersion::new(1, 2);
+        let v2_0 = IsaVersion::new(2, 0);
+
+        assert!(v1_2.is_newer_than_or_equal(v1_0));
+        assert!(v1_2.is_newer_than_or_equal(v1_2));
+        assert!(!v1_0.is_newer_than_or_equal(v1_2));
+
+        assert!(v1_0.is_older_than(v1_2));
+        assert!(!v1_2.is_older_than(v1_0));
+        assert!(v1_2.is_older_than(v2_0));
+    }
+
+    #[test]
+    fn version_display_format() {
+        let v = IsaVersion::new(1, 5);
+        assert_eq!(v.to_string(), "1.5");
+    }
+
+    #[test]
+    fn version_parsing() {
+        let v: IsaVersion = "1.5".parse().unwrap();
+        assert_eq!(v.major, 1);
+        assert_eq!(v.minor, 5);
+    }
+
+    #[test]
+    fn version_parsing_errors() {
+        assert!("1".parse::<IsaVersion>().is_err());
+        assert!("1.2.3".parse::<IsaVersion>().is_err());
+        assert!("a.b".parse::<IsaVersion>().is_err());
+    }
+
+    #[test]
+    fn version_ordering() {
+        let v1_0 = IsaVersion::new(1, 0);
+        let v1_2 = IsaVersion::new(1, 2);
+        let v2_0 = IsaVersion::new(2, 0);
+
+        assert!(v1_0 < v1_2);
+        assert!(v1_2 < v2_0);
+        assert!(v1_0 < v2_0);
+    }
+
+    #[test]
+    fn boundary_max_version_numbers() {
+        let v_max = IsaVersion::new(u16::MAX, u16::MAX);
+        assert_eq!(v_max.major, u16::MAX);
+        assert_eq!(v_max.minor, u16::MAX);
+        assert!(v_max.is_compatible_with(v_max));
+    }
+}

crates/jxcl-lexer/Cargo.toml

@@ -0,0 +1,9 @@
+[package]
+name = "jxcl-lexer"
+version = "0.1.0"
+edition = "2021"
+description = "Tokenizes assembly source text."
+license = "AGPL-3.0-only OR LicenseRef-Commercial"
+
+[dependencies]
+jxcl-errors = { path = "../jxcl-errors" }

crates/jxcl-lexer/README.md

@@ -0,0 +1,36 @@
+# jxcl-lexer
+
+Tokenizes assembly source text.
+
+## Architecture
+
+**Owns:** The Token type and lexer.
+
+**Category:** toolchain · **Source:** extraction:jxcl/src/assembler/lexer.rs
+
+## Public API
+
+`lex`, `Token`
+
+## Dependencies
+
+Workspace crates:
+
+- `jxcl-errors`
+
+External crates:
+
+*(none)*
+
+## Testing
+
+Planned test kinds: unit, boundary.
+
+## Status
+
+`planned` in `docs/crates.toml` -- see
+`docs/CRATE_GENERATION_PLAN.md` for the implementation batch schedule.
+
+## License
+
+AGPLv3 / Commercial dual-license. See `LICENSE-AGPL`, `LICENSE-COMMERCIAL`, and `LICENSE-NOTICE` at the repository root.

crates/jxcl-lexer/src/lib.rs

@@ -0,0 +1,271 @@
+// Copyright (C) 2026 ERRANT DIGITAL INSTITUTE OF TECHNOLOGY (SEIT NGO) % SNAPKITTY COLLECTIVE
+// SPDX-License-Identifier: AGPL-3.0-only OR LicenseRef-Commercial
+// See LICENSE-AGPL and LICENSE-COMMERCIAL in this repository for license terms.
+
+//! Tokenizes assembly source text.
+//!
+//! Owns: the [`Token`] type and [`lex`]/[`lex_line`] -- extracted, near
+//! verbatim, from `jxcl`'s original `src/assembler/lexer.rs`. JXCL
+//! assembly is line-oriented -- every statement (label, directive, or
+//! instruction) occupies exactly one line -- which keeps the grammar
+//! simple and error locations exact.
+//!
+//! `docs/crates.toml` lists `jxcl-errors` as this crate's one dependency
+//! (for the crate-wide error type). At the time this crate was
+//! implemented, `jxcl-errors` was still a scaffolded placeholder with no
+//! public items, so [`LexError`] is a small local error type scoped to
+//! lexing, matching the shape (`kind`/`line`/`reason`) of what
+//! `jxcl-errors`'s `AssemblerErrorKind` variants would produce. Once
+//! `jxcl-errors` lands, this can become a thin wrapper (or direct
+//! re-export) instead of an independent type.
+
+#![forbid(unsafe_code)]
+
+use std::fmt;
+
+#[derive(Debug, Clone, PartialEq, Eq)]
+pub enum Token {
+    /// A bare word: mnemonic, register name, label, or constant reference.
+    Ident(String),
+    /// A directive keyword, without its leading `.` (e.g. `.data` -> `"data"`).
+    Directive(String),
+    /// A numeric literal (decimal, `0x` hex, or `0b` binary), already parsed.
+    Number(i128),
+    Comma,
+    Colon,
+    LBracket,
+    RBracket,
+    Plus,
+    Minus,
+}
+
+#[derive(Debug, Clone, PartialEq, Eq)]
+pub enum LexErrorKind {
+    MalformedImmediate,
+    UnexpectedToken,
+}
+
+#[derive(Debug, Clone, PartialEq, Eq)]
+pub struct LexError {
+    pub kind: LexErrorKind,
+    pub line: usize,
+    pub reason: String,
+}
+
+impl fmt::Display for LexError {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        write!(
+            f,
+            "lex error at line {}: {:?}: {}",
+            self.line, self.kind, self.reason
+        )
+    }
+}
+impl std::error::Error for LexError {}
+
+fn is_ident_start(c: char) -> bool {
+    c.is_ascii_alphabetic() || c == '_'
+}
+fn is_ident_continue(c: char) -> bool {
+    c.is_ascii_alphanumeric() || c == '_'
+}
+
+fn parse_number(text: &str, line: usize) -> Result<i128, LexError> {
+    let bad = |reason: String| LexError {
+        kind: LexErrorKind::MalformedImmediate,
+        line,
+        reason,
+    };
+    if let Some(hex) = text.strip_prefix("0x").or_else(|| text.strip_prefix("0X")) {
+        i128::from_str_radix(hex, 16)
+            .map_err(|e| bad(format!("invalid hex literal {:?}: {}", text, e)))
+    } else if let Some(bin) = text.strip_prefix("0b").or_else(|| text.strip_prefix("0B")) {
+        i128::from_str_radix(bin, 2)
+            .map_err(|e| bad(format!("invalid binary literal {:?}: {}", text, e)))
+    } else {
+        text.parse::<i128>()
+            .map_err(|e| bad(format!("invalid decimal literal {:?}: {}", text, e)))
+    }
+}
+
+/// Tokenize one line of JXCL assembly source. `;` begins a line comment
+/// that runs to end of line.
+pub fn lex_line(line_text: &str, line: usize) -> Result<Vec<Token>, LexError> {
+    let mut tokens = Vec::new();
+    let chars: Vec<char> = line_text.chars().collect();
+    let mut i = 0usize;
+
+    while i < chars.len() {
+        let c = chars[i];
+        match c {
+            ' ' | '\t' | '\r' => {
+                i += 1;
+            }
+            ';' => break, // rest of line is a comment
+            ',' => {
+                tokens.push(Token::Comma);
+                i += 1;
+            }
+            ':' => {
+                tokens.push(Token::Colon);
+                i += 1;
+            }
+            '[' => {
+                tokens.push(Token::LBracket);
+                i += 1;
+            }
+            ']' => {
+                tokens.push(Token::RBracket);
+                i += 1;
+            }
+            '+' => {
+                tokens.push(Token::Plus);
+                i += 1;
+            }
+            '-' => {
+                tokens.push(Token::Minus);
+                i += 1;
+            }
+            '.' => {
+                let start = i + 1;
+                let mut j = start;
+                while j < chars.len() && is_ident_continue(chars[j]) {
+                    j += 1;
+                }
+                if j == start {
+                    return Err(LexError {
+                        kind: LexErrorKind::UnexpectedToken,
+                        line,
+                        reason: "'.' not followed by a directive name".into(),
+                    });
+                }
+                tokens.push(Token::Directive(chars[start..j].iter().collect()));
+                i = j;
+            }
+            c if c.is_ascii_digit() => {
+                let start = i;
+                let mut j = i + 1;
+                while j < chars.len() && is_ident_continue(chars[j]) {
+                    j += 1;
+                }
+                let text: String = chars[start..j].iter().collect();
+                tokens.push(Token::Number(parse_number(&text, line)?));
+                i = j;
+            }
+            c if is_ident_start(c) => {
+                let start = i;
+                let mut j = i + 1;
+                while j < chars.len() && is_ident_continue(chars[j]) {
+                    j += 1;
+                }
+                tokens.push(Token::Ident(chars[start..j].iter().collect()));
+                i = j;
+            }
+            other => {
+                return Err(LexError {
+                    kind: LexErrorKind::UnexpectedToken,
+                    line,
+                    reason: format!("unexpected character {:?}", other),
+                });
+            }
+        }
+    }
+
+    Ok(tokens)
+}
+
+/// Tokenize a complete multi-line source file, one line at a time.
+/// Returns one entry per source line, in order, as `(1-based line number,
+/// that line's tokens)`. A blank or comment-only line yields an empty
+/// token vector rather than being skipped, so line numbers in the result
+/// always match the source file exactly.
+pub fn lex(source: &str) -> Result<Vec<(usize, Vec<Token>)>, LexError> {
+    let mut out = Vec::new();
+    for (idx, raw_line) in source.lines().enumerate() {
+        let line_no = idx + 1;
+        out.push((line_no, lex_line(raw_line, line_no)?));
+    }
+    Ok(out)
+}
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+
+    #[test]
+    fn tokenizes_instruction_line() {
+        let toks = lex_line("    MOVI R1, 10", 1).unwrap();
+        assert_eq!(
+            toks,
+            vec![
+                Token::Ident("MOVI".into()),
+                Token::Ident("R1".into()),
+                Token::Comma,
+                Token::Number(10),
+            ]
+        );
+    }
+
+    #[test]
+    fn tokenizes_label() {
+        let toks = lex_line("start:", 1).unwrap();
+        assert_eq!(toks, vec![Token::Ident("start".into()), Token::Colon]);
+    }
+
+    #[test]
+    fn tokenizes_hex_and_binary() {
+        let toks = lex_line("0x1A 0b1010", 1).unwrap();
+        assert_eq!(toks, vec![Token::Number(0x1A), Token::Number(0b1010)]);
+    }
+
+    #[test]
+    fn strips_comments() {
+        let toks = lex_line("HALT ; stop here", 1).unwrap();
+        assert_eq!(toks, vec![Token::Ident("HALT".into())]);
+    }
+
+    #[test]
+    fn tokenizes_memory_operand() {
+        let toks = lex_line("[R2+8]", 1).unwrap();
+        assert_eq!(
+            toks,
+            vec![
+                Token::LBracket,
+                Token::Ident("R2".into()),
+                Token::Plus,
+                Token::Number(8),
+                Token::RBracket
+            ]
+        );
+    }
+
+    #[test]
+    fn tokenizes_directive() {
+        let toks = lex_line(".data", 1).unwrap();
+        assert_eq!(toks, vec![Token::Directive("data".into())]);
+    }
+
+    #[test]
+    fn lex_whole_source_preserves_line_numbers() {
+        let src = "MOVI R1, 1\n\nHALT\n";
+        let lines = lex(src).unwrap();
+        assert_eq!(lines.len(), 3);
+        assert_eq!(lines[0].0, 1);
+        assert_eq!(lines[1].0, 2);
+        assert!(lines[1].1.is_empty());
+        assert_eq!(lines[2].0, 3);
+        assert_eq!(lines[2].1, vec![Token::Ident("HALT".into())]);
+    }
+
+    #[test]
+    fn rejects_unexpected_character() {
+        let err = lex_line("MOVI R1, @", 1).unwrap_err();
+        assert_eq!(err.kind, LexErrorKind::UnexpectedToken);
+    }
+
+    #[test]
+    fn rejects_malformed_number() {
+        let err = lex_line("0xZZ", 1).unwrap_err();
+        assert_eq!(err.kind, LexErrorKind::MalformedImmediate);
+    }
+}

crates/jxcl-linker/Cargo.toml

@@ -0,0 +1,13 @@
+[package]
+name = "jxcl-linker"
+version = "0.1.0"
+edition = "2021"
+description = "Resolves symbols and applies relocations across one or more object files into a single linked binary container."
+license = "AGPL-3.0-only OR LicenseRef-Commercial"
+
+[dependencies]
+jxcl-object = { path = "../jxcl-object" }
+jxcl-symbols = { path = "../jxcl-symbols" }
+jxcl-relocations = { path = "../jxcl-relocations" }
+jxcl-binary = { path = "../jxcl-binary" }
+jxcl-errors = { path = "../jxcl-errors" }

crates/jxcl-linker/README.md

@@ -0,0 +1,40 @@
+# jxcl-linker
+
+Resolves symbols and applies relocations across one or more object files into a single linked binary container.
+
+## Architecture
+
+**Owns:** link(&[ObjectFile]) -> BinaryContainer.
+
+**Category:** toolchain · **Source:** new
+
+## Public API
+
+`link`
+
+## Dependencies
+
+Workspace crates:
+
+- `jxcl-object`
+- `jxcl-symbols`
+- `jxcl-relocations`
+- `jxcl-binary`
+- `jxcl-errors`
+
+External crates:
+
+*(none)*
+
+## Testing
+
+Planned test kinds: unit, integration, error-path.
+
+## Status
+
+`planned` in `docs/crates.toml` -- see
+`docs/CRATE_GENERATION_PLAN.md` for the implementation batch schedule.
+
+## License
+
+AGPLv3 / Commercial dual-license. See `LICENSE-AGPL`, `LICENSE-COMMERCIAL`, and `LICENSE-NOTICE` at the repository root.

crates/jxcl-linker/src/lib.rs

@@ -0,0 +1,335 @@
+// Copyright (C) 2026 ERRANT DIGITAL INSTITUTE OF TECHNOLOGY (SEIT NGO) % SNAPKITTY COLLECTIVE
+// SPDX-License-Identifier: AGPL-3.0-only OR LicenseRef-Commercial
+// See LICENSE-AGPL and LICENSE-COMMERCIAL in this repository for license terms.
+
+//! Resolves symbols and applies relocations across one or more object
+//! files into a single linked binary container.
+//!
+//! New functionality (see `jxcl-object`'s module docs for why there is
+//! no pre-expansion ground truth to extract this from -- the original
+//! `jxcl` assembler always went straight from source to a finished
+//! binary in one step, with no separate-compilation/linking phase at
+//! all).
+//!
+//! ## Layout
+//!
+//! [`link`] concatenates every object file's code section, in the order
+//! given, into one combined code section, and likewise for data
+//! sections. Matching `jxcl-binary`'s convention, the combined data
+//! section is placed immediately after the combined code section, so a
+//! `Data`-section symbol's final absolute address is
+//! `total_code_size + <that object's data section's start within the
+//! combined data section> + <the symbol's original section-local
+//! address>`.
+//!
+//! Every object's [`jxcl_symbols::SymbolTable`] entries are re-based to
+//! these final absolute addresses and merged into one combined table; a
+//! name defined in more than one input object is a
+//! [`LinkErrorKind::DuplicateSymbol`] error (linking never silently
+//! picks one definition over another). Every relocation is then applied,
+//! via [`jxcl_relocations::apply_relocation`], against the combined
+//! buffer at its correctly re-based absolute offset; a relocation whose
+//! symbol resolves in no object is a [`LinkErrorKind::UndefinedSymbol`]
+//! error.
+//!
+//! At most one input object may set
+//! [`jxcl_object::ObjectFile::entry_symbol`]; if none do, the linked
+//! program's entry point defaults to `0` (matching the assembler's own
+//! default).
+#![forbid(unsafe_code)]
+
+use std::fmt;
+
+use jxcl_binary::BinaryContainer;
+use jxcl_object::{ObjectFile, RelocationTarget};
+use jxcl_relocations::{apply_relocation, Relocation};
+use jxcl_symbols::SymbolTable;
+
+#[derive(Debug, Clone, PartialEq, Eq)]
+pub enum LinkErrorKind {
+    /// The same symbol name was defined by more than one input object.
+    DuplicateSymbol,
+    /// A relocation (or the entry point) referenced a symbol no input
+    /// object defines.
+    UndefinedSymbol,
+    /// More than one input object set `entry_symbol`.
+    MultipleEntryPoints,
+    /// A relocation's field didn't fit the resolved address (e.g. a
+    /// `PcRelative32` displacement that overflowed 32 bits).
+    RelocationFailed,
+}
+
+#[derive(Debug, Clone, PartialEq, Eq)]
+pub struct LinkError {
+    pub kind: LinkErrorKind,
+    pub reason: String,
+}
+
+impl fmt::Display for LinkError {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        write!(f, "link error: {:?}: {}", self.kind, self.reason)
+    }
+}
+impl std::error::Error for LinkError {}
+
+fn err(kind: LinkErrorKind, reason: impl Into<String>) -> LinkError {
+    LinkError {
+        kind,
+        reason: reason.into(),
+    }
+}
+
+/// Link one or more relocatable object files into a single runnable
+/// [`BinaryContainer`].
+pub fn link(objects: &[ObjectFile]) -> Result<BinaryContainer, LinkError> {
+    // Pass 1: compute each object's placement (running code/data offsets)
+    // and the combined section sizes.
+    let mut code_offsets = Vec::with_capacity(objects.len());
+    let mut data_offsets = Vec::with_capacity(objects.len());
+    let mut code_cursor: u64 = 0;
+    let mut data_cursor: u64 = 0;
+    for obj in objects {
+        code_offsets.push(code_cursor);
+        data_offsets.push(data_cursor);
+        code_cursor += obj.code.len() as u64;
+        data_cursor += obj.data.len() as u64;
+    }
+    let total_code_size = code_cursor;
+
+    // Pass 2: build the combined symbol table at final absolute addresses.
+    let mut combined_symbols = SymbolTable::new();
+    for (i, obj) in objects.iter().enumerate() {
+        for sym in obj.symbols.iter() {
+            let abs_address = match sym.section {
+                jxcl_symbols::SymbolSection::Code => code_offsets[i] + sym.address,
+                jxcl_symbols::SymbolSection::Data => {
+                    total_code_size + data_offsets[i] + sym.address
+                }
+            };
+            combined_symbols
+                .define(sym.name.clone(), abs_address, sym.section)
+                .map_err(|_| {
+                    err(
+                        LinkErrorKind::DuplicateSymbol,
+                        format!(
+                            "symbol {:?} is defined in more than one object file",
+                            sym.name
+                        ),
+                    )
+                })?;
+        }
+    }
+
+    // Pass 3: concatenate code and data into one combined buffer (code
+    // first, data immediately after -- matching jxcl-binary's layout).
+    let mut combined: Vec<u8> = Vec::with_capacity(
+        objects.iter().map(|o| o.code.len()).sum::<usize>()
+            + objects.iter().map(|o| o.data.len()).sum::<usize>(),
+    );
+    for obj in objects {
+        combined.extend_from_slice(&obj.code);
+    }
+    for obj in objects {
+        combined.extend_from_slice(&obj.data);
+    }
+
+    // Pass 4: apply every relocation at its re-based absolute offset.
+    for (i, obj) in objects.iter().enumerate() {
+        for tr in &obj.relocations {
+            let abs_offset = match tr.target {
+                RelocationTarget::Code => code_offsets[i] + tr.relocation.offset,
+                RelocationTarget::Data => total_code_size + data_offsets[i] + tr.relocation.offset,
+            };
+            let resolved = combined_symbols
+                .resolve(&tr.relocation.symbol)
+                .ok_or_else(|| {
+                    err(
+                        LinkErrorKind::UndefinedSymbol,
+                        format!("undefined symbol {:?}", tr.relocation.symbol),
+                    )
+                })?;
+            let reloc =
+                Relocation::new(abs_offset, tr.relocation.kind, tr.relocation.symbol.clone());
+            apply_relocation(&mut combined, &reloc, resolved.address)
+                .map_err(|e| err(LinkErrorKind::RelocationFailed, e.to_string()))?;
+        }
+    }
+
+    // Pass 5: resolve the entry point, if any object nominated one.
+    let mut entry_symbol: Option<&str> = None;
+    for obj in objects {
+        if let Some(name) = &obj.entry_symbol {
+            if entry_symbol.is_some() {
+                return Err(err(
+                    LinkErrorKind::MultipleEntryPoints,
+                    "more than one object file set an entry symbol",
+                ));
+            }
+            entry_symbol = Some(name.as_str());
+        }
+    }
+    let entry_point = match entry_symbol {
+        Some(name) => {
+            combined_symbols
+                .resolve(name)
+                .ok_or_else(|| {
+                    err(
+                        LinkErrorKind::UndefinedSymbol,
+                        format!("entry symbol {:?} is undefined", name),
+                    )
+                })?
+                .address
+        }
+        None => 0,
+    };
+
+    let (code, data) = combined.split_at(total_code_size as usize);
+    Ok(BinaryContainer::new(
+        entry_point,
+        code.to_vec(),
+        data.to_vec(),
+    ))
+}
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+    use jxcl_object::TargetedRelocation;
+    use jxcl_relocations::RelocationKind;
+    use jxcl_symbols::SymbolSection;
+
+    #[test]
+    fn links_a_single_object_with_no_relocations() {
+        let obj = ObjectFile::new(vec![0x60], vec![]).with_entry_symbol("start");
+        let mut obj = obj;
+        obj.symbols.define("start", 0, SymbolSection::Code).unwrap();
+        let bin = link(&[obj]).unwrap();
+        assert_eq!(bin.entry_point, 0);
+        assert_eq!(bin.code, vec![0x60]);
+    }
+
+    #[test]
+    fn defaults_entry_point_to_zero_when_unset() {
+        let obj = ObjectFile::new(vec![0x60], vec![]);
+        let bin = link(&[obj]).unwrap();
+        assert_eq!(bin.entry_point, 0);
+    }
+
+    #[test]
+    fn links_two_objects_with_a_cross_reference() {
+        // Object A: a 5-byte "CALL helper" placeholder instruction
+        // (1 opcode byte + 4-byte PC-relative displacement) followed by
+        // a 1-byte HALT. It references "helper", defined in object B.
+        let mut a = ObjectFile::new(vec![0xABu8, 0, 0, 0, 0, 0x60], vec![]);
+        a.relocations.push(TargetedRelocation::new(
+            jxcl_object::RelocationTarget::Code,
+            jxcl_relocations::Relocation::new(1, RelocationKind::PcRelative32, "helper"),
+        ));
+        a = a.with_entry_symbol("main");
+        a.symbols.define("main", 0, SymbolSection::Code).unwrap();
+
+        // Object B: "helper" is a single HALT at its own offset 0.
+        let mut b = ObjectFile::new(vec![0x60], vec![]);
+        b.symbols.define("helper", 0, SymbolSection::Code).unwrap();
+
+        let bin = link(&[a, b]).unwrap();
+        // Object A occupies bytes [0, 6); object B is appended at 6.
+        assert_eq!(bin.code.len(), 7);
+        assert_eq!(bin.entry_point, 0);
+        // The relocation field is bytes [1, 5); pc_after_fetch = 5;
+        // helper's final absolute address is 6 (start of object B's code).
+        let disp = i32::from_le_bytes(bin.code[1..5].try_into().unwrap());
+        assert_eq!(disp, 1); // 6 - 5
+        assert_eq!(bin.code[6], 0x60);
+    }
+
+    #[test]
+    fn cross_referencing_a_data_symbol_resolves_past_the_combined_code_section() {
+        // A single object whose code references a data-section symbol
+        // via an absolute-64 relocation (like MOVI loading a label's
+        // address). Exercises the code-size-relative data placement.
+        let mut obj = ObjectFile::new(
+            vec![0x02u8, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0x60], // MOVI-shaped + HALT
+            vec![0xEFu8, 0xBE, 0, 0, 0, 0, 0, 0],
+        );
+        obj.relocations.push(TargetedRelocation::new(
+            jxcl_object::RelocationTarget::Code,
+            jxcl_relocations::Relocation::new(2, RelocationKind::Absolute64, "buffer"),
+        ));
+        obj.symbols
+            .define("buffer", 0, SymbolSection::Data)
+            .unwrap();
+
+        let bin = link(&[obj]).unwrap();
+        assert_eq!(bin.code.len(), 11);
+        assert_eq!(bin.data.len(), 8);
+        // "buffer"'s absolute address equals the total code size (11).
+        let patched = u64::from_le_bytes(bin.code[2..10].try_into().unwrap());
+        assert_eq!(patched, 11);
+    }
+
+    #[test]
+    fn undefined_symbol_relocation_is_an_error() {
+        let mut obj = ObjectFile::new(vec![0xABu8, 0, 0, 0, 0], vec![]);
+        obj.relocations.push(TargetedRelocation::new(
+            jxcl_object::RelocationTarget::Code,
+            jxcl_relocations::Relocation::new(1, RelocationKind::PcRelative32, "nowhere"),
+        ));
+        let err = link(&[obj]).unwrap_err();
+        assert_eq!(err.kind, LinkErrorKind::UndefinedSymbol);
+    }
+
+    #[test]
+    fn duplicate_symbol_across_objects_is_an_error() {
+        let mut a = ObjectFile::new(vec![0x60], vec![]);
+        a.symbols.define("dup", 0, SymbolSection::Code).unwrap();
+        let mut b = ObjectFile::new(vec![0x60], vec![]);
+        b.symbols.define("dup", 0, SymbolSection::Code).unwrap();
+
+        let err = link(&[a, b]).unwrap_err();
+        assert_eq!(err.kind, LinkErrorKind::DuplicateSymbol);
+    }
+
+    #[test]
+    fn multiple_entry_points_is_an_error() {
+        let mut a = ObjectFile::new(vec![0x60], vec![]).with_entry_symbol("a_main");
+        a.symbols.define("a_main", 0, SymbolSection::Code).unwrap();
+        let mut b = ObjectFile::new(vec![0x60], vec![]).with_entry_symbol("b_main");
+        b.symbols.define("b_main", 0, SymbolSection::Code).unwrap();
+
+        let err = link(&[a, b]).unwrap_err();
+        assert_eq!(err.kind, LinkErrorKind::MultipleEntryPoints);
+    }
+
+    #[test]
+    fn undefined_entry_symbol_is_an_error() {
+        let obj = ObjectFile::new(vec![0x60], vec![]).with_entry_symbol("ghost");
+        let err = link(&[obj]).unwrap_err();
+        assert_eq!(err.kind, LinkErrorKind::UndefinedSymbol);
+    }
+
+    #[test]
+    fn relocation_displacement_out_of_range_is_an_error() {
+        let mut obj = ObjectFile::new(vec![0xABu8, 0, 0, 0, 0], vec![]);
+        obj.relocations.push(TargetedRelocation::new(
+            jxcl_object::RelocationTarget::Code,
+            jxcl_relocations::Relocation::new(1, RelocationKind::PcRelative32, "far"),
+        ));
+        // A symbol whose address is nowhere near the relocation site --
+        // still representable as a u64, but its computed displacement
+        // overflows i32.
+        obj.symbols
+            .define("far", u64::MAX / 2, SymbolSection::Code)
+            .unwrap();
+        let err = link(&[obj]).unwrap_err();
+        assert_eq!(err.kind, LinkErrorKind::RelocationFailed);
+    }
+
+    #[test]
+    fn empty_object_list_links_to_an_empty_binary() {
+        let bin = link(&[]).unwrap();
+        assert!(bin.code.is_empty());
+        assert!(bin.data.is_empty());
+        assert_eq!(bin.entry_point, 0);
+    }
+}

crates/jxcl-load-store/Cargo.toml

@@ -0,0 +1,15 @@
+[package]
+name = "jxcl-load-store"
+version = "0.1.0"
+edition = "2021"
+description = "Typed, sign-extension-aware load/store helpers (u8/u16/u32/u64 and signed variants) between raw memory and the execution engine."
+license = "AGPL-3.0-only OR LicenseRef-Commercial"
+
+[dependencies]
+jxcl-memory = { path = "../jxcl-memory" }
+jxcl-endian = { path = "../jxcl-endian" }
+jxcl-exceptions = { path = "../jxcl-exceptions" }
+jxcl-types = { path = "../jxcl-types" }
+
+[dev-dependencies]
+jxcl-errors = { path = "../jxcl-errors" }

crates/jxcl-load-store/README.md

@@ -0,0 +1,51 @@
+# jxcl-load-store
+
+Typed, sign-extension-aware load/store helpers (u8/u16/u32/u64 and signed variants) between raw memory and the execution engine.
+
+## Architecture
+
+**Owns:** `load_u8/16/32/64`, `store_u8/16/32/64` and their signed
+counterparts (`load_i8/16/32/64`, `store_i8/16/32/64`).
+
+**Category:** memory · **Source:** new (generalizes
+`crates/jxcl/src/execution.rs`'s direct `state.memory.read64`/`write64`
++ `try_mem!` fault-conversion pattern to every width and to signed
+values, converting into `jxcl-exceptions::Exception`).
+
+## Public API
+
+`load_u8`, `load_u16`, `load_u32`, `load_u64`, `load_i8`, `load_i16`,
+`load_i32`, `load_i64`, `store_u8`, `store_u16`, `store_u32`,
+`store_u64`, `store_i8`, `store_i16`, `store_i32`, `store_i64` -- all
+operating on a `jxcl-memory::Memory` at a `jxcl-types::Address`,
+returning `Result<_, jxcl_exceptions::Exception>`.
+
+## Dependencies
+
+Workspace crates:
+
+- `jxcl-memory`
+- `jxcl-endian`
+- `jxcl-exceptions`
+- `jxcl-types`
+
+External crates:
+
+*(none)*
+
+## Testing
+
+`cargo test -p jxcl-load-store`: unit tests for unsigned roundtrip at
+every width, correct sign extension on signed loads, truncation on
+signed stores, `MemoryFault` -> `Exception` conversion on out-of-bounds
+and misaligned access, and a property-style roundtrip sweep over several
+representative values (including width extremes) for both unsigned and
+signed 64-bit paths.
+
+## Status
+
+`implemented`.
+
+## License
+
+AGPLv3 / Commercial dual-license. See `LICENSE-AGPL`, `LICENSE-COMMERCIAL`, and `LICENSE-NOTICE` at the repository root.